Matthew D. Sandifer

Array ( [id] => 19506638 [patent_doc_number] => 12118059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Projection-based techniques for updating singular value decomposition in evolving data sets [patent_app_type] => utility [patent_app_number] => 17/335928 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7368 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 434 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18463448 [patent_doc_number] => 11687738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Chopper stabilized bias unit element with binary weighted charge transfer capacitors [patent_app_type] => utility [patent_app_number] => 17/334899 [patent_app_country] => US [patent_app_date] => 2021-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 8213 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17334899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17261522 [patent_doc_number] => 20210374507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => Method for Pulse-Based Convolution for Near-Sensor Processing [patent_app_type] => utility [patent_app_number] => 17/332540 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17332540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19740184 [patent_doc_number] => 12217019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Processing-in-memory devices having multiplication-and-accumulation circuits [patent_app_type] => utility [patent_app_number] => 17/331426 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10507 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17069234 [patent_doc_number] => 20210271450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => PROCESSING CORE WITH DATA ASSOCIATIVE ADAPTIVE ROUNDING [patent_app_type] => utility [patent_app_number] => 17/321925 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321925 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19841894 [patent_doc_number] => 12254284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Multiplication-and-accumulation circuits and processing-in-memory devices having the same [patent_app_type] => utility [patent_app_number] => 17/319717 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10471 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17319717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19538578 [patent_doc_number] => 12131131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Random number generator circuit [patent_app_type] => utility [patent_app_number] => 17/317349 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3626 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317349 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19963848 [patent_doc_number] => 12333357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Memory bit cell for in-memory computation [patent_app_type] => utility [patent_app_number] => 17/317844 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5496 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18703522 [patent_doc_number] => 11790035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => System, method, and recording medium for mirroring matrices for batched cholesky decomposition on a graphic processing unit [patent_app_type] => utility [patent_app_number] => 17/315710 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4387 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19934012 [patent_doc_number] => 12307217 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-20 [patent_title] => Dynamic adjustment of floating point exponent bias for exponent compression [patent_app_type] => utility [patent_app_number] => 17/313224 [patent_app_country] => US [patent_app_date] => 2021-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 1169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17313224 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18422643 [patent_doc_number] => 20230177107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => ARRANGEMENT AND METHOD FOR PERFORMING A VECTOR-MATRIX MULTIPLICATION BY MEANS OF CAPACITIVE OR RESISTIVE SYNAPTIC COMPONENTS [patent_app_type] => utility [patent_app_number] => 17/997394 [patent_app_country] => US [patent_app_date] => 2021-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17997394 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18136091 [patent_doc_number] => 11561768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Non-linear feedback shift register [patent_app_type] => utility [patent_app_number] => 17/241517 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 10251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17241517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17401794 [patent_doc_number] => 20220043884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => SYSTEM AND METHOD FOR AN OPTIMIZED WINOGRAD CONVOLUTION ACCELERATOR [patent_app_type] => utility [patent_app_number] => 17/237989 [patent_app_country] => US [patent_app_date] => 2021-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17237989 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18104461 [patent_doc_number] => 11544349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Method for combining analog neural net with FPGA routing in a monolithic integrated circuit [patent_app_type] => utility [patent_app_number] => 17/232075 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6550 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232075 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16979802 [patent_doc_number] => 20210224039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => MULTIPLICATION AND ACCUMULATION (MAC) OPERATOR AND PROCESSING-IN-MEMORY (PIM) DEVICE INCLUDING THE MAC OPERATOR [patent_app_type] => utility [patent_app_number] => 17/225915 [patent_app_country] => US [patent_app_date] => 2021-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 48423 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -41 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19933697 [patent_doc_number] => 12306901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Operation accelerator, processing method, and related device [patent_app_type] => utility [patent_app_number] => 17/224643 [patent_app_country] => US [patent_app_date] => 2021-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 7800 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 409 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17144256 [patent_doc_number] => 20210312269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => NEURAL NETWORK DEVICE FOR NEURAL NETWORK OPERATION, METHOD OF OPERATING NEURAL NETWORK DEVICE, AND APPLICATION PROCESSOR INCLUDING NEURAL NETWORK DEVICE [patent_app_type] => utility [patent_app_number] => 17/223324 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223324 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17316920 [patent_doc_number] => 20210405969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => COMPUTER-READABLE RECORDING MEDIUM RECORDING ARITHMETIC PROCESSING PROGRAM, ARITHMETIC PROCESSING METHOD, AND ARITHMETIC PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 17/216736 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18561501 [patent_doc_number] => 11726744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Integrated circuits with machine learning extensions [patent_app_type] => utility [patent_app_number] => 17/214526 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19764998 [patent_doc_number] => 12223289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Neural network device for neural network operation, operating method of the neural network device, and application processor including the same [patent_app_type] => utility [patent_app_number] => 17/212474 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 18092 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212474 [rel_patent_id] =>[rel_patent_doc_number] =>)