Search

Matthew E. Gordon

Examiner (ID: 3833, Phone: (571)270-7432 , Office: P/2892 )

Most Active Art Unit
2892
Art Unit(s)
2892
Total Applications
1057
Issued Applications
812
Pending Applications
12
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18977293 [patent_doc_number] => 20240057385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/383265 [patent_app_country] => US [patent_app_date] => 2023-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18383265 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/383265
Display device having crack prevention portions on a side portion and method of fabricating the same Oct 23, 2023 Issued
Array ( [id] => 18961256 [patent_doc_number] => 20240049583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 18/382051 [patent_app_country] => US [patent_app_date] => 2023-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18382051 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/382051
Display panel Oct 18, 2023 Issued
Array ( [id] => 18943548 [patent_doc_number] => 20240038687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS [patent_app_type] => utility [patent_app_number] => 18/380022 [patent_app_country] => US [patent_app_date] => 2023-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6820 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18380022 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/380022
Heterogeneous nested interposer package for IC chips Oct 12, 2023 Issued
Array ( [id] => 19370622 [patent_doc_number] => 12062716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Semiconductor device including source pad region and drain pad region configured to improve current uniformity and reduce resistance [patent_app_type] => utility [patent_app_number] => 18/482025 [patent_app_country] => US [patent_app_date] => 2023-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6507 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18482025 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/482025
Semiconductor device including source pad region and drain pad region configured to improve current uniformity and reduce resistance Oct 5, 2023 Issued
Array ( [id] => 19356890 [patent_doc_number] => 12057346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Semiconductor device including metal interconnections having sidewall spacers thereon, and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 18/243096 [patent_app_country] => US [patent_app_date] => 2023-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2345 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18243096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/243096
Semiconductor device including metal interconnections having sidewall spacers thereon, and method for fabricating the same Sep 5, 2023 Issued
Array ( [id] => 19444470 [patent_doc_number] => 12094759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Method for transferring blocks from a donor substrate onto a receiver substrate by implanting ions in the donor substrate through a mask, bonding the donor substrate to the receiver substrate, and detaching the donor substrate along an embrittlement plane [patent_app_type] => utility [patent_app_number] => 18/451486 [patent_app_country] => US [patent_app_date] => 2023-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 25 [patent_no_of_words] => 6121 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451486 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/451486
Method for transferring blocks from a donor substrate onto a receiver substrate by implanting ions in the donor substrate through a mask, bonding the donor substrate to the receiver substrate, and detaching the donor substrate along an embrittlement plane Aug 16, 2023 Issued
Array ( [id] => 18906244 [patent_doc_number] => 20240021729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => FIN FIELD-EFFECT TRANSISTOR DEVICE HAVING HYBRID WORK FUNCTION LAYER STACK [patent_app_type] => utility [patent_app_number] => 18/357794 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357794 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357794
Fin field-effect transistor device having hybrid work function layer stack Jul 23, 2023 Issued
Array ( [id] => 19262622 [patent_doc_number] => 12022708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Display device including connection wiring part laterally adjacent to driving voltage wiring [patent_app_type] => utility [patent_app_number] => 18/357044 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 14743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357044 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357044
Display device including connection wiring part laterally adjacent to driving voltage wiring Jul 20, 2023 Issued
Array ( [id] => 18759737 [patent_doc_number] => 20230363227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => ORGANIC LIGHT-EMITTING DIODE DISPLAY SUBSTRATE, DISPLAY DEVICE, AND METHOD MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/354218 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354218 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354218
White organic light-emitting diode display substrate including switching TFT and light-shielding layer arranged to prevent negative drift Jul 17, 2023 Issued
Array ( [id] => 19173728 [patent_doc_number] => 20240159702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => METHODS AND APPARATUS FOR MEASURING ANALYTES USING LARGE SCALE FET ARRAYS [patent_app_type] => utility [patent_app_number] => 18/353017 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 48073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18353017 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/353017
Methods and apparatus for measuring analytes using large scale FET arrays Jul 13, 2023 Issued
Array ( [id] => 18743590 [patent_doc_number] => 20230352578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => TRENCH-GATE FIELD EFFECT TRANSISTOR WITH IMPROVED ELECTRICAL PERFORMANCES AND CORRESPONDING MANUFACTURING PROCESS [patent_app_type] => utility [patent_app_number] => 18/348990 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348990 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348990
Trench-gate field effect transistor with improved electrical performances and corresponding manufacturing process Jul 6, 2023 Issued
Array ( [id] => 18743378 [patent_doc_number] => 20230352366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => HEAT DISSIPATION STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/347013 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347013 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347013
Heat dissipation structures for three-dimensional system on integrated chip structure Jul 4, 2023 Issued
Array ( [id] => 19138004 [patent_doc_number] => 11972979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => 1D vertical edge blocking (VEB) via and plug [patent_app_type] => utility [patent_app_number] => 18/207047 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 7013 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18207047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/207047
1D vertical edge blocking (VEB) via and plug Jun 6, 2023 Issued
Array ( [id] => 19108654 [patent_doc_number] => 11961768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => CMOS FinFET structures including work-function materials having different proportions of crystalline orientations and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/312647 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 8251 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312647 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312647
CMOS FinFET structures including work-function materials having different proportions of crystalline orientations and methods of forming the same May 4, 2023 Issued
Array ( [id] => 18557054 [patent_doc_number] => 20230255073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/305816 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305816 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/305816
Display device including side terminal disposed along an inclined side surface thereof, and method of manufacturing the same Apr 23, 2023 Issued
Array ( [id] => 19123573 [patent_doc_number] => 11967567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Semiconductor package with EMI shield and fabricating method thereof [patent_app_type] => utility [patent_app_number] => 18/138325 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 4847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138325 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/138325
Semiconductor package with EMI shield and fabricating method thereof Apr 23, 2023 Issued
Array ( [id] => 18535025 [patent_doc_number] => 20230240106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/193418 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9836 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18193418 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/193418
Display device including transistor with vias contacting active layer through etch stop layer, and method of manufacturing same Mar 29, 2023 Issued
Array ( [id] => 18516358 [patent_doc_number] => 20230232681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => METHOD OF MANUFACTURING DISPLAY PANEL AND DISPLAY PANEL MANUFACTURED BY THE SAME [patent_app_type] => utility [patent_app_number] => 18/121646 [patent_app_country] => US [patent_app_date] => 2023-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18121646 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/121646
Method of manufacturing display panel with circuit-layer stack including metal, oxide, and capping layers, and display panel manufactured by the same Mar 14, 2023 Issued
Array ( [id] => 19001016 [patent_doc_number] => 11917895 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Display device including galvanic reaction-patterned electrodes, and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/178683 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 10535 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18178683 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/178683
Display device including galvanic reaction-patterned electrodes, and method of manufacturing the same Mar 5, 2023 Issued
Array ( [id] => 19155122 [patent_doc_number] => 11980059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Array substrate and manufacturing method thereof including via hole to facilitate dehydrogenation, display panel, and display device [patent_app_type] => utility [patent_app_number] => 18/110157 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 10290 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110157 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110157
Array substrate and manufacturing method thereof including via hole to facilitate dehydrogenation, display panel, and display device Feb 14, 2023 Issued
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