Search

Matthew E. Gordon

Examiner (ID: 7811, Phone: (571)270-7432 , Office: P/2892 )

Most Active Art Unit
2892
Art Unit(s)
2892
Total Applications
1057
Issued Applications
812
Pending Applications
12
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15581247 [patent_doc_number] => 10581019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Organic EL element having reduced electric power consumption by optimizing film thicknesses thereof and method of manufacturing same [patent_app_type] => utility [patent_app_number] => 15/715800 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 8169 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715800 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715800
Organic EL element having reduced electric power consumption by optimizing film thicknesses thereof and method of manufacturing same Sep 25, 2017 Issued
Array ( [id] => 14769457 [patent_doc_number] => 10396130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Display substrate including sub-electrodes having trapezium shape and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/715125 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3666 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715125 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715125
Display substrate including sub-electrodes having trapezium shape and method for manufacturing the same Sep 24, 2017 Issued
Array ( [id] => 12616056 [patent_doc_number] => 20180097182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => ORGANIC OPTOELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 15/714317 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714317 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714317
ORGANIC OPTOELECTRONIC DEVICE Sep 24, 2017 Abandoned
Array ( [id] => 13668061 [patent_doc_number] => 10164214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Display panel having organic buffer layer including droplet micro-structures for decentralizing stress and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/714081 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2684 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714081 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714081
Display panel having organic buffer layer including droplet micro-structures for decentralizing stress and method for manufacturing the same Sep 24, 2017 Issued
Array ( [id] => 12141211 [patent_doc_number] => 20180019294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'Display Panel and Display Device' [patent_app_type] => utility [patent_app_number] => 15/713691 [patent_app_country] => US [patent_app_date] => 2017-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5770 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713691 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/713691
Display panel including power supply compensation film having reduced sheet resistance arranged on opposite surface of substrate from power supply line layer Sep 23, 2017 Issued
Array ( [id] => 15234471 [patent_doc_number] => 10504966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Light-emitting device comprising transparent conductive films having different thicknesses [patent_app_type] => utility [patent_app_number] => 15/695308 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 38 [patent_no_of_words] => 23774 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695308 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695308
Light-emitting device comprising transparent conductive films having different thicknesses Sep 4, 2017 Issued
Array ( [id] => 16433086 [patent_doc_number] => 10833185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Heterojunction semiconductor device having source and drain pads with improved current crowding [patent_app_type] => utility [patent_app_number] => 15/678102 [patent_app_country] => US [patent_app_date] => 2017-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678102 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678102
Heterojunction semiconductor device having source and drain pads with improved current crowding Aug 14, 2017 Issued
Array ( [id] => 12396462 [patent_doc_number] => 09966412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Method for reducing optical cross-talk in image sensors [patent_app_type] => utility [patent_app_number] => 15/647968 [patent_app_country] => US [patent_app_date] => 2017-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4789 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15647968 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/647968
Method for reducing optical cross-talk in image sensors Jul 11, 2017 Issued
Array ( [id] => 13667069 [patent_doc_number] => 10163711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Methods of packaging semiconductor devices including placing semiconductor devices into die caves [patent_app_type] => utility [patent_app_number] => 15/613992 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3832 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15613992 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/613992
Methods of packaging semiconductor devices including placing semiconductor devices into die caves Jun 4, 2017 Issued
Array ( [id] => 11959438 [patent_doc_number] => 20170263590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'SEMICONDUCTOR DEVICE COMPRISING PN JUNCTION DIODE AND SCHOTTKY BARRIER DIODE' [patent_app_type] => utility [patent_app_number] => 15/609407 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609407 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/609407
Semiconductor device comprising PN junction diode and schottky barrier diode May 30, 2017 Issued
Array ( [id] => 16545206 [patent_doc_number] => 20200411621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/073815 [patent_app_country] => US [patent_app_date] => 2017-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16073815 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/073815
Display device configured to switch between single-sided and double-sided display May 28, 2017 Issued
Array ( [id] => 13350125 [patent_doc_number] => 20180226602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => ORGANIC LIGHT EMITTING DIODE AND MANUFACTURING METHOD OF THE SAME, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/569100 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4017 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15569100 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/569100
Organic light emitting diode having connecting layer including material corresponding to carriers in carrier transport layer May 11, 2017 Issued
Array ( [id] => 13350129 [patent_doc_number] => 20180226604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => DISPLAY SUBSTRATE, DISPLAY PANEL, DISPLAY APPARATUS, AND METHOD OF FABRICATING DISPLAY SUBSTRATE AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 15/571120 [patent_app_country] => US [patent_app_date] => 2017-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15571120 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/571120
Display panel having passivation layer with protruding portions in peripheral area for sealant May 9, 2017 Issued
Array ( [id] => 11869631 [patent_doc_number] => 20170236916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING SENSE INSULATED-GATE BIPOLAR TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 15/585492 [patent_app_country] => US [patent_app_date] => 2017-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11150 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15585492 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/585492
Semiconductor device including sense insulated-gate bipolar transistor May 2, 2017 Issued
Array ( [id] => 11974772 [patent_doc_number] => 20170278926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'SHALLOW TRENCH ISOLATION TRENCHES AND METHODS FOR NAND MEMORY' [patent_app_type] => utility [patent_app_number] => 15/582632 [patent_app_country] => US [patent_app_date] => 2017-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7517 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15582632 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/582632
SHALLOW TRENCH ISOLATION TRENCHES AND METHODS FOR NAND MEMORY Apr 28, 2017 Abandoned
Array ( [id] => 11840098 [patent_doc_number] => 20170221818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'LOGIC CELL, SEMICONDUCTOR DEVICE INCLUDING LOGIC CELL, AND METHOD OF MANUFACTURING THE LOGIC CELL AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/493279 [patent_app_country] => US [patent_app_date] => 2017-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15493279 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/493279
Logic cell including single layer via contact and deep via contact Apr 20, 2017 Issued
Array ( [id] => 12294474 [patent_doc_number] => 09935179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Method for making semiconductor device with filled gate line end recesses [patent_app_type] => utility [patent_app_number] => 15/472556 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 34 [patent_no_of_words] => 2103 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15472556 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/472556
Method for making semiconductor device with filled gate line end recesses Mar 28, 2017 Issued
Array ( [id] => 11959457 [patent_doc_number] => 20170263609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/469721 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 15573 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15469721 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/469721
SEMICONDUCTOR DEVICE Mar 26, 2017 Abandoned
Array ( [id] => 11733034 [patent_doc_number] => 20170194477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/468133 [patent_app_country] => US [patent_app_date] => 2017-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15468133 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/468133
Power semiconductor device integrated with ESD protection circuit under source pad, drain pad, and/or gate pad Mar 23, 2017 Issued
Array ( [id] => 15260297 [patent_doc_number] => 20190378882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => Display And Method For Manufacturing The Same [patent_app_type] => utility [patent_app_number] => 15/781631 [patent_app_country] => US [patent_app_date] => 2017-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15781631 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/781631
Display device including integrated circuit ports connected to sub-pixels using cross diagonal wires Mar 14, 2017 Issued
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