
Matthew E. Gordon
Examiner (ID: 7811, Phone: (571)270-7432 , Office: P/2892 )
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2892 |
| Total Applications | 1057 |
| Issued Applications | 812 |
| Pending Applications | 12 |
| Abandoned Applications | 247 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10577071
[patent_doc_number] => 09299721
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-29
[patent_title] => 'Method for making semiconductor device with different fin sets'
[patent_app_type] => utility
[patent_app_number] => 14/280998
[patent_app_country] => US
[patent_app_date] => 2014-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 2600
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14280998
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/280998 | Method for making semiconductor device with different fin sets | May 18, 2014 | Issued |
Array
(
[id] => 10448140
[patent_doc_number] => 20150333155
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-19
[patent_title] => 'METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH FILLED GATE LINE END RECESSES'
[patent_app_type] => utility
[patent_app_number] => 14/281021
[patent_app_country] => US
[patent_app_date] => 2014-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 2075
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281021
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/281021 | Method for making semiconductor device with filled gate line end recesses | May 18, 2014 | Issued |
Array
(
[id] => 10447912
[patent_doc_number] => 20150332926
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-19
[patent_title] => 'Method of Forming High-K Gates Dielectrics'
[patent_app_type] => utility
[patent_app_number] => 14/280654
[patent_app_country] => US
[patent_app_date] => 2014-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2247
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14280654
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/280654 | Method of Forming High-K Gates Dielectrics | May 17, 2014 | Abandoned |
Array
(
[id] => 10611082
[patent_doc_number] => 09331126
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-03
[patent_title] => 'Method for fabricating flexible display using a shape memory alloy film'
[patent_app_type] => utility
[patent_app_number] => 14/280578
[patent_app_country] => US
[patent_app_date] => 2014-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2427
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14280578
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/280578 | Method for fabricating flexible display using a shape memory alloy film | May 16, 2014 | Issued |
Array
(
[id] => 10447949
[patent_doc_number] => 20150332962
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-19
[patent_title] => 'Structure and Method for Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 14/280196
[patent_app_country] => US
[patent_app_date] => 2014-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 6545
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14280196
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/280196 | Method of forming semiconductor device including source/drain contact having height below gate stack | May 15, 2014 | Issued |
Array
(
[id] => 16047927
[patent_doc_number] => 10685846
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-16
[patent_title] => Semiconductor integrated circuit fabrication with pattern-reversing process
[patent_app_type] => utility
[patent_app_number] => 14/280182
[patent_app_country] => US
[patent_app_date] => 2014-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 4519
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 462
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14280182
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/280182 | Semiconductor integrated circuit fabrication with pattern-reversing process | May 15, 2014 | Issued |
Array
(
[id] => 9699081
[patent_doc_number] => 20140248766
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-04
[patent_title] => 'THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/276124
[patent_app_country] => US
[patent_app_date] => 2014-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 9751
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14276124
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/276124 | Three-dimensional semiconductor device and method of fabricating the same | May 12, 2014 | Issued |
Array
(
[id] => 10659655
[patent_doc_number] => 20160005799
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-01-07
[patent_title] => 'THIN FILM TRANSISTOR, TFT ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/429867
[patent_app_country] => US
[patent_app_date] => 2014-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6224
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14429867
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/429867 | THIN FILM TRANSISTOR, TFT ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE | Apr 29, 2014 | Abandoned |
Array
(
[id] => 12114981
[patent_doc_number] => 09870974
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-16
[patent_title] => 'Power conversion apparatus including wedge inserts'
[patent_app_type] => utility
[patent_app_number] => 15/123355
[patent_app_country] => US
[patent_app_date] => 2014-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 39
[patent_no_of_words] => 11902
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15123355
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/123355 | Power conversion apparatus including wedge inserts | Mar 27, 2014 | Issued |
Array
(
[id] => 10674284
[patent_doc_number] => 20160020429
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-01-21
[patent_title] => 'METHOD FOR MANUFACTURING ORGANIC LIGHT EMITTING ELEMENT, AND ORGANIC LIGHT EMITTING ELEMENT'
[patent_app_type] => utility
[patent_app_number] => 14/769682
[patent_app_country] => US
[patent_app_date] => 2014-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 26317
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14769682
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/769682 | Method for manufacturing organic light emitting element including light extracting layer formed by irradiating coating solution | Feb 19, 2014 | Issued |
Array
(
[id] => 10336729
[patent_doc_number] => 20150221734
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-06
[patent_title] => 'THICKER BOTTOM OXIDE FOR REDUCED MILLER CAPACITANCE IN TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET)'
[patent_app_type] => utility
[patent_app_number] => 14/171777
[patent_app_country] => US
[patent_app_date] => 2014-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 5087
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14171777
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/171777 | THICKER BOTTOM OXIDE FOR REDUCED MILLER CAPACITANCE IN TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) | Feb 3, 2014 | Abandoned |
Array
(
[id] => 10336729
[patent_doc_number] => 20150221734
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-06
[patent_title] => 'THICKER BOTTOM OXIDE FOR REDUCED MILLER CAPACITANCE IN TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET)'
[patent_app_type] => utility
[patent_app_number] => 14/171777
[patent_app_country] => US
[patent_app_date] => 2014-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 5087
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14171777
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/171777 | THICKER BOTTOM OXIDE FOR REDUCED MILLER CAPACITANCE IN TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) | Feb 3, 2014 | Abandoned |
Array
(
[id] => 11776078
[patent_doc_number] => 09385028
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-07-05
[patent_title] => 'Air gap process'
[patent_app_type] => utility
[patent_app_number] => 14/171400
[patent_app_country] => US
[patent_app_date] => 2014-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 10307
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14171400
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/171400 | Air gap process | Feb 2, 2014 | Issued |
Array
(
[id] => 10336732
[patent_doc_number] => 20150221737
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-06
[patent_title] => 'SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/170959
[patent_app_country] => US
[patent_app_date] => 2014-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6633
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14170959
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/170959 | Semiconductor device including spacers having different dimensions | Feb 2, 2014 | Issued |
Array
(
[id] => 10336510
[patent_doc_number] => 20150221515
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-06
[patent_title] => 'METHOD AND APPARATUS FOR COOLING WAFER IN ION IMPLANTATION PROCESS'
[patent_app_type] => utility
[patent_app_number] => 14/170837
[patent_app_country] => US
[patent_app_date] => 2014-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4869
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14170837
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/170837 | Method and apparatus for cooling wafer in ion implantation process | Feb 2, 2014 | Issued |
Array
(
[id] => 9671600
[patent_doc_number] => 20140235463
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-21
[patent_title] => 'METHODS AND APPARATUS FOR MEASURING ANALYTES'
[patent_app_type] => utility
[patent_app_number] => 14/160472
[patent_app_country] => US
[patent_app_date] => 2014-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 131
[patent_figures_cnt] => 131
[patent_no_of_words] => 105661
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14160472
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/160472 | Apparatus for measuring analytes including chemical sensor array | Jan 20, 2014 | Issued |
Array
(
[id] => 9449518
[patent_doc_number] => 20140120688
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-01
[patent_title] => 'DEEP ISOLATION TRENCH STRUCTURE AND DEEP TRENCH CAPACITOR ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 14/146198
[patent_app_country] => US
[patent_app_date] => 2014-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 7629
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14146198
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/146198 | Deep isolation trench structure and deep trench capacitor on a semiconductor-on-insulator substrate | Jan 1, 2014 | Issued |
Array
(
[id] => 10277408
[patent_doc_number] => 20150162405
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-11
[patent_title] => 'TRANSISTOR WITH A DIFFUSION BARRIER'
[patent_app_type] => utility
[patent_app_number] => 14/100760
[patent_app_country] => US
[patent_app_date] => 2013-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9310
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100760
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/100760 | Transistor with a diffusion barrier | Dec 8, 2013 | Issued |
Array
(
[id] => 9768096
[patent_doc_number] => 20140291758
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-10-02
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING PLANAR SOURCE ELECTRODE'
[patent_app_type] => utility
[patent_app_number] => 14/100455
[patent_app_country] => US
[patent_app_date] => 2013-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
[patent_figures_cnt] => 36
[patent_no_of_words] => 10775
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100455
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/100455 | Semiconductor device having planar source electrode | Dec 8, 2013 | Issued |
Array
(
[id] => 10577297
[patent_doc_number] => 09299951
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-29
[patent_title] => 'Display panel including multilayer diffusion barrier'
[patent_app_type] => utility
[patent_app_number] => 14/100525
[patent_app_country] => US
[patent_app_date] => 2013-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5998
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100525
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/100525 | Display panel including multilayer diffusion barrier | Dec 8, 2013 | Issued |