Search

Matthew E. Gordon

Examiner (ID: 7811, Phone: (571)270-7432 , Office: P/2892 )

Most Active Art Unit
2892
Art Unit(s)
2892
Total Applications
1057
Issued Applications
812
Pending Applications
12
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8335637 [patent_doc_number] => 20120202342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/450329 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5500 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450329 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/450329
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Apr 17, 2012 Abandoned
Array ( [id] => 9107770 [patent_doc_number] => 20130280902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'STRATIFIED GATE DIELECTRIC STACK FOR GATE DIELECTRIC LEAKAGE REDUCTION' [patent_app_type] => utility [patent_app_number] => 13/449647 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11551 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449647 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/449647
Stratified gate dielectric stack for gate dielectric leakage reduction Apr 17, 2012 Issued
Array ( [id] => 9104692 [patent_doc_number] => 20130277823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'Split Loop Cut Pattern For Spacer Process' [patent_app_type] => utility [patent_app_number] => 13/449650 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 15517 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449650 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/449650
Split loop cut pattern for spacer process Apr 17, 2012 Issued
Array ( [id] => 9094400 [patent_doc_number] => 20130273711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'METHOD OF FORMING A FINFET DEVICE' [patent_app_type] => utility [patent_app_number] => 13/449118 [patent_app_country] => US [patent_app_date] => 2012-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 4959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449118 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/449118
Method of forming a FinFET device Apr 16, 2012 Issued
Array ( [id] => 8489629 [patent_doc_number] => 20120289036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'SURFACE DOSE RETENTION OF DOPANTS BY PRE-AMORPHIZATION AND POST IMPLANT PASSIVATION TREATMENTS' [patent_app_type] => utility [patent_app_number] => 13/449180 [patent_app_country] => US [patent_app_date] => 2012-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2885 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449180 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/449180
SURFACE DOSE RETENTION OF DOPANTS BY PRE-AMORPHIZATION AND POST IMPLANT PASSIVATION TREATMENTS Apr 16, 2012 Abandoned
Array ( [id] => 8321909 [patent_doc_number] => 20120194316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'FUSE BOX STRUCTURE IN SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/440899 [patent_app_country] => US [patent_app_date] => 2012-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2619 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13440899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/440899
FUSE BOX STRUCTURE IN SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME Apr 4, 2012 Abandoned
Array ( [id] => 11214744 [patent_doc_number] => 09443784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Semiconductor module including plate-shaped insulating members having different thickness' [patent_app_type] => utility [patent_app_number] => 14/371854 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7413 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14371854 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/371854
Semiconductor module including plate-shaped insulating members having different thickness Mar 8, 2012 Issued
Array ( [id] => 9828157 [patent_doc_number] => 08937386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-20 [patent_title] => 'Chip package structure with ENIG plating' [patent_app_type] => utility [patent_app_number] => 13/414461 [patent_app_country] => US [patent_app_date] => 2012-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 4911 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 469 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13414461 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/414461
Chip package structure with ENIG plating Mar 6, 2012 Issued
Array ( [id] => 8240424 [patent_doc_number] => 20120149160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'LAYOUT METHOD OF SEMICONDUCTOR DEVICE WITH JUNCTION DIODE FOR PREVENTING DAMAGE DUE TO PLASMA CHARGE' [patent_app_type] => utility [patent_app_number] => 13/364362 [patent_app_country] => US [patent_app_date] => 2012-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3480 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13364362 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/364362
Layout method of semiconductor device with junction diode for preventing damage due to plasma charge Feb 1, 2012 Issued
Array ( [id] => 9118152 [patent_doc_number] => 20130285074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'LUMINESCENT DEVICE AND MANUFACTURING METHOD FOR LUMINESCENT DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/978677 [patent_app_country] => US [patent_app_date] => 2012-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6752 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13978677 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/978677
Luminescent device and manufacturing method for luminescent device and semiconductor device Jan 10, 2012 Issued
Array ( [id] => 8172532 [patent_doc_number] => 20120107965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/345948 [patent_app_country] => US [patent_app_date] => 2012-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 17184 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20120107965.pdf [firstpage_image] =>[orig_patent_app_number] => 13345948 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/345948
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Jan 8, 2012 Abandoned
Array ( [id] => 10118897 [patent_doc_number] => 09153791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Organic EL display panel' [patent_app_type] => utility [patent_app_number] => 13/978601 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 7582 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13978601 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/978601
Organic EL display panel Dec 21, 2011 Issued
Array ( [id] => 8134025 [patent_doc_number] => 20120091563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'METHOD FOR INSULATING A SEMICONDUCTOR MATERIAL IN A TRENCH FROM A SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/332466 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3899 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20120091563.pdf [firstpage_image] =>[orig_patent_app_number] => 13332466 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/332466
METHOD FOR INSULATING A SEMICONDUCTOR MATERIAL IN A TRENCH FROM A SUBSTRATE Dec 20, 2011 Abandoned
Array ( [id] => 8863130 [patent_doc_number] => 20130146833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'MEMORY CELLS HAVING A PLURALITY OF HEATERS' [patent_app_type] => utility [patent_app_number] => 13/316133 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4798 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13316133 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/316133
Memory cells having a plurality of heaters Dec 8, 2011 Issued
Array ( [id] => 9663010 [patent_doc_number] => 08809994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Deep isolation trench structure and deep trench capacitor on a semiconductor-on-insulator substrate' [patent_app_type] => utility [patent_app_number] => 13/316104 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7592 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13316104 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/316104
Deep isolation trench structure and deep trench capacitor on a semiconductor-on-insulator substrate Dec 8, 2011 Issued
Array ( [id] => 8863337 [patent_doc_number] => 20130147040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'MEMS CHIP SCALE PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/316119 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2010 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13316119 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/316119
MEMS CHIP SCALE PACKAGE Dec 8, 2011 Abandoned
Array ( [id] => 8705455 [patent_doc_number] => 20130062744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'POWER MODULE PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/316121 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3338 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13316121 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/316121
POWER MODULE PACKAGE Dec 8, 2011 Abandoned
Array ( [id] => 8767574 [patent_doc_number] => 20130095611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'Packaging Methods for Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 13/276143 [patent_app_country] => US [patent_app_date] => 2011-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13276143 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/276143
Packaging methods for semiconductor devices including forming trenches in workpiece to separate adjacent packaging substrates Oct 17, 2011 Issued
Array ( [id] => 9482910 [patent_doc_number] => 08728861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Fabrication method for ZnO thin film transistors using etch-stop layer' [patent_app_type] => utility [patent_app_number] => 13/271310 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 4330 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13271310 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/271310
Fabrication method for ZnO thin film transistors using etch-stop layer Oct 11, 2011 Issued
Array ( [id] => 8120807 [patent_doc_number] => 20120084954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'METHOD OF MANUFACTURING SOLID ELECTROLYTIC CAPACITOR' [patent_app_type] => utility [patent_app_number] => 13/270951 [patent_app_country] => US [patent_app_date] => 2011-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2138 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20120084954.pdf [firstpage_image] =>[orig_patent_app_number] => 13270951 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/270951
METHOD OF MANUFACTURING SOLID ELECTROLYTIC CAPACITOR Oct 10, 2011 Abandoned
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