Search

Matthew E. Gordon

Examiner (ID: 7811, Phone: (571)270-7432 , Office: P/2892 )

Most Active Art Unit
2892
Art Unit(s)
2892
Total Applications
1057
Issued Applications
812
Pending Applications
12
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8211086 [patent_doc_number] => 20120129728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'Methods and Apparatus for Measuring Analytes Using Large Scale FET Arrays' [patent_app_type] => utility [patent_app_number] => 13/019463 [patent_app_country] => US [patent_app_date] => 2011-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 72 [patent_no_of_words] => 50449 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20120129728.pdf [firstpage_image] =>[orig_patent_app_number] => 13019463 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/019463
Methods and apparatus for measuring analytes using large scale FET arrays Feb 1, 2011 Issued
Array ( [id] => 9958632 [patent_doc_number] => 09006844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-14 [patent_title] => 'Process and structure for high temperature selective fusion bonding' [patent_app_type] => utility [patent_app_number] => 13/574343 [patent_app_country] => US [patent_app_date] => 2011-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5392 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13574343 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/574343
Process and structure for high temperature selective fusion bonding Jan 25, 2011 Issued
Array ( [id] => 5963408 [patent_doc_number] => 20110147881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'HYBRID SUBSTRATE WITH IMPROVED ISOLATION AND SIMPLIFIED METHOD FOR PRODUCING A HYBRID SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/976250 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5181 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20110147881.pdf [firstpage_image] =>[orig_patent_app_number] => 12976250 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/976250
Hybrid substrate with improved isolation and simplified method for producing a hybrid substrate Dec 21, 2010 Issued
Array ( [id] => 7479842 [patent_doc_number] => 20110248277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'METHOD OF CRYSTALIZING AMORPHOUS SILICON LAYER, METHOD OF MANUFACTURING THIN FILM TRANSISTOR USING THE SAME, AND THIN FILM TRANSISTOR USING THE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 12/975809 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9588 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248277.pdf [firstpage_image] =>[orig_patent_app_number] => 12975809 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/975809
METHOD OF CRYSTALIZING AMORPHOUS SILICON LAYER, METHOD OF MANUFACTURING THIN FILM TRANSISTOR USING THE SAME, AND THIN FILM TRANSISTOR USING THE MANUFACTURING METHOD Dec 21, 2010 Abandoned
Array ( [id] => 5971077 [patent_doc_number] => 20110151607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'METHOD FOR MANUFACTURING A METAL AND DIELECTRIC NANOSTRUCTURES ELECTRODE FOR COLORED FILTERING IN AN OLED AND METHOD FOR MANUFACTURING AN OLED' [patent_app_type] => utility [patent_app_number] => 12/976265 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10342 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20110151607.pdf [firstpage_image] =>[orig_patent_app_number] => 12976265 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/976265
METHOD FOR MANUFACTURING A METAL AND DIELECTRIC NANOSTRUCTURES ELECTRODE FOR COLORED FILTERING IN AN OLED AND METHOD FOR MANUFACTURING AN OLED Dec 21, 2010 Abandoned
Array ( [id] => 8897249 [patent_doc_number] => 08476772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Semiconductor device and method of forming base substrate with recesses for capturing bumped semiconductor die' [patent_app_type] => utility [patent_app_number] => 12/953812 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 5265 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12953812 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953812
Semiconductor device and method of forming base substrate with recesses for capturing bumped semiconductor die Nov 23, 2010 Issued
Array ( [id] => 8205134 [patent_doc_number] => 20120126318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'Integrated Circuit Including Field Effect Transistor' [patent_app_type] => utility [patent_app_number] => 12/953682 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4188 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20120126318.pdf [firstpage_image] =>[orig_patent_app_number] => 12953682 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953682
Vertical power semiconductor carrier having laterally isolated circuit areas Nov 23, 2010 Issued
Array ( [id] => 6208382 [patent_doc_number] => 20110133305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'SEMICONDUCTOR CHIP FOR SUPPRESSING ELECTROMAGNETIC WAVE' [patent_app_type] => utility [patent_app_number] => 12/953742 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3248 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20110133305.pdf [firstpage_image] =>[orig_patent_app_number] => 12953742 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953742
SEMICONDUCTOR CHIP FOR SUPPRESSING ELECTROMAGNETIC WAVE Nov 23, 2010 Abandoned
Array ( [id] => 6177568 [patent_doc_number] => 20110121342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'ORGANIC LIGHT EMITTING DIODE LIGHTING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/953572 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3865 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20110121342.pdf [firstpage_image] =>[orig_patent_app_number] => 12953572 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953572
ORGANIC LIGHT EMITTING DIODE LIGHTING APPARATUS Nov 23, 2010 Abandoned
Array ( [id] => 9167276 [patent_doc_number] => 08592959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Semiconductor device mounted on a wiring board having a cap' [patent_app_type] => utility [patent_app_number] => 12/953808 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6304 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12953808 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953808
Semiconductor device mounted on a wiring board having a cap Nov 23, 2010 Issued
Array ( [id] => 8205229 [patent_doc_number] => 20120126378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'SEMICONDUCTOR DEVICE PACKAGE WITH ELECTROMAGNETIC SHIELDING' [patent_app_type] => utility [patent_app_number] => 12/953578 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4502 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20120126378.pdf [firstpage_image] =>[orig_patent_app_number] => 12953578 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953578
SEMICONDUCTOR DEVICE PACKAGE WITH ELECTROMAGNETIC SHIELDING Nov 23, 2010 Abandoned
Array ( [id] => 8205156 [patent_doc_number] => 20120126334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'BREAKDOWN VOLTAGE IMPROVEMENT WITH A FLOATING SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/953665 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20120126334.pdf [firstpage_image] =>[orig_patent_app_number] => 12953665 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953665
BREAKDOWN VOLTAGE IMPROVEMENT WITH A FLOATING SUBSTRATE Nov 23, 2010 Abandoned
Array ( [id] => 8205250 [patent_doc_number] => 20120126387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'ENHANCED HEAT SPREADER FOR USE IN AN ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/953669 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20120126387.pdf [firstpage_image] =>[orig_patent_app_number] => 12953669 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953669
ENHANCED HEAT SPREADER FOR USE IN AN ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME Nov 23, 2010 Abandoned
Array ( [id] => 8205204 [patent_doc_number] => 20120126364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'MITIGATION OF DETRIMENTAL BREAKDOWN OF A HIGH DIELECTRIC CONSTANT METAL-INSULATOR-METAL CAPACITOR IN A CAPACITOR BANK' [patent_app_type] => utility [patent_app_number] => 12/953624 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3622 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20120126364.pdf [firstpage_image] =>[orig_patent_app_number] => 12953624 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953624
Mitigation of detrimental breakdown of a high dielectric constant metal-insulator-metal capacitor in a capacitor bank Nov 23, 2010 Issued
Array ( [id] => 8204985 [patent_doc_number] => 20120126239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'LAYER STRUCTURES FOR CONTROLLING STRESS OF HETEROEPITAXIALLY GROWN III-NITRIDE LAYERS' [patent_app_type] => utility [patent_app_number] => 12/953769 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4476 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20120126239.pdf [firstpage_image] =>[orig_patent_app_number] => 12953769 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953769
LAYER STRUCTURES FOR CONTROLLING STRESS OF HETEROEPITAXIALLY GROWN III-NITRIDE LAYERS Nov 23, 2010 Abandoned
Array ( [id] => 6075379 [patent_doc_number] => 20110140269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/926558 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7693 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20110140269.pdf [firstpage_image] =>[orig_patent_app_number] => 12926558 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/926558
Semiconductor device and method for manufacturing the same Nov 23, 2010 Abandoned
Array ( [id] => 5963176 [patent_doc_number] => 20110147801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/953748 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 9736 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20110147801.pdf [firstpage_image] =>[orig_patent_app_number] => 12953748 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953748
Three-dimensional semiconductor device including a mold structure providing gap regions and an interconnection structure including a plurality of interconnection patterns formed in the gap regions Nov 23, 2010 Issued
Array ( [id] => 6177543 [patent_doc_number] => 20110121326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'Submount Having Reflective Cu-Ni-Ag Pads Formed Using Electroless Deposition' [patent_app_type] => utility [patent_app_number] => 12/953358 [patent_app_country] => US [patent_app_date] => 2010-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4579 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20110121326.pdf [firstpage_image] =>[orig_patent_app_number] => 12953358 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953358
Submount Having Reflective Cu-Ni-Ag Pads Formed Using Electroless Deposition Nov 22, 2010 Abandoned
Array ( [id] => 8205139 [patent_doc_number] => 20120126323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING A SPLIT GATE AND A SUPER-JUNCTION STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/953200 [patent_app_country] => US [patent_app_date] => 2010-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5008 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20120126323.pdf [firstpage_image] =>[orig_patent_app_number] => 12953200 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953200
Semiconductor device having a split gate and a super-junction structure Nov 22, 2010 Issued
Array ( [id] => 6202095 [patent_doc_number] => 20110064881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'PLASTIC ELECTRONIC COMPONENT PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/950528 [patent_app_country] => US [patent_app_date] => 2010-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4902 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20110064881.pdf [firstpage_image] =>[orig_patent_app_number] => 12950528 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/950528
Plastic electronic component package Nov 18, 2010 Issued
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