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Matthew E. Gordon

Examiner (ID: 7811, Phone: (571)270-7432 , Office: P/2892 )

Most Active Art Unit
2892
Art Unit(s)
2892
Total Applications
1057
Issued Applications
812
Pending Applications
12
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4913031 [patent_doc_number] => 20080093630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'Heterostructure Field Effect Transistor' [patent_app_type] => utility [patent_app_number] => 11/571671 [patent_app_country] => US [patent_app_date] => 2005-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2055 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20080093630.pdf [firstpage_image] =>[orig_patent_app_number] => 11571671 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/571671
Heterostructure Field Effect Transistor Jul 5, 2005 Abandoned
Array ( [id] => 5578705 [patent_doc_number] => 20090174051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'Semiconductor package and semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/585092 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7125 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20090174051.pdf [firstpage_image] =>[orig_patent_app_number] => 10585092 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/585092
Semiconductor package and semiconductor device Jan 11, 2005 Abandoned
Array ( [id] => 5043650 [patent_doc_number] => 20070262321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Lateral Field Effect Transistor and Its Fabrication Comprising a Spacer Layer Above and Below the Channel Layer' [patent_app_type] => utility [patent_app_number] => 11/661962 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4290 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20070262321.pdf [firstpage_image] =>[orig_patent_app_number] => 11661962 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/661962
Lateral field effect transistor and its fabrication comprising a spacer layer above and below the channel layer Aug 31, 2004 Issued
Array ( [id] => 9552927 [patent_doc_number] => 08759981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Method for the production of a fixed connection between two layers of a multilayer system, and multilayer system' [patent_app_type] => utility [patent_app_number] => 10/524672 [patent_app_country] => US [patent_app_date] => 2003-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2817 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10524672 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/524672
Method for the production of a fixed connection between two layers of a multilayer system, and multilayer system Aug 11, 2003 Issued
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