Search

Matthew E. Warren

Examiner (ID: 9271, Phone: (571)272-1737 , Office: P/2815 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2817
Total Applications
1856
Issued Applications
1508
Pending Applications
127
Abandoned Applications
248

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11425021 [patent_doc_number] => 20170033167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'Organic Light Emitting Device' [patent_app_type] => utility [patent_app_number] => 15/295901 [patent_app_country] => US [patent_app_date] => 2016-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 9432 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15295901 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/295901
Organic light emitting device Oct 16, 2016 Issued
Array ( [id] => 11424895 [patent_doc_number] => 20170033040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'HIGH SPEED, HIGH DENSITY, LOW POWER DIE INTERCONNECT SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/293561 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 19630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15293561 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/293561
High speed, high density, low power die interconnect system Oct 13, 2016 Issued
Array ( [id] => 11405032 [patent_doc_number] => 20170025570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-26 [patent_title] => 'Light-Emitting Semiconductor Chip' [patent_app_type] => utility [patent_app_number] => 15/287140 [patent_app_country] => US [patent_app_date] => 2016-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5363 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15287140 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/287140
Light-emitting semiconductor chip Oct 5, 2016 Issued
Array ( [id] => 16637971 [patent_doc_number] => 10916486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Semiconductor device including silane based adhesion promoter and method of making [patent_app_type] => utility [patent_app_number] => 16/335527 [patent_app_country] => US [patent_app_date] => 2016-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7730 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16335527 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/335527
Semiconductor device including silane based adhesion promoter and method of making Sep 25, 2016 Issued
Array ( [id] => 11385939 [patent_doc_number] => 20170011994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/272553 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 19612 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15272553 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/272553
Semiconductor device and manufacturing method thereof Sep 21, 2016 Issued
Array ( [id] => 11366892 [patent_doc_number] => 20170004873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'STRUCTURE AND METHOD FOR ADJUSTING THRESHOLD VOLTAGE OF THE ARRAY OF TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 15/266519 [patent_app_country] => US [patent_app_date] => 2016-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 16142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15266519 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/266519
Structure and method for adjusting threshold voltage of the array of transistors Sep 14, 2016 Issued
Array ( [id] => 11353764 [patent_doc_number] => 20160372504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/256987 [patent_app_country] => US [patent_app_date] => 2016-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 36912 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15256987 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/256987
Solid-state imaging device, camera module and electronic apparatus Sep 5, 2016 Issued
Array ( [id] => 13893685 [patent_doc_number] => 10199398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Display device with different circuit groups [patent_app_type] => utility [patent_app_number] => 15/254102 [patent_app_country] => US [patent_app_date] => 2016-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3045 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15254102 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/254102
Display device with different circuit groups Aug 31, 2016 Issued
Array ( [id] => 12026924 [patent_doc_number] => 20170317023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'PACKAGED SEMICONDUCTOR DEVICES WITH WIRELESS CHARGING MEANS' [patent_app_type] => utility [patent_app_number] => 15/254135 [patent_app_country] => US [patent_app_date] => 2016-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4874 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15254135 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/254135
Packaged semiconductor devices with wireless charging means Aug 31, 2016 Issued
Array ( [id] => 11439437 [patent_doc_number] => 20170040458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/242802 [patent_app_country] => US [patent_app_date] => 2016-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 29760 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15242802 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/242802
Semiconductor device Aug 21, 2016 Issued
Array ( [id] => 11293892 [patent_doc_number] => 20160343824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'MULTI-LAYER GATE DIELECTRIC' [patent_app_type] => utility [patent_app_number] => 15/225785 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225785 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/225785
MULTI-LAYER GATE DIELECTRIC Jul 31, 2016 Abandoned
Array ( [id] => 12229948 [patent_doc_number] => 09917197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Thin film element, semiconductor device, and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 15/219764 [patent_app_country] => US [patent_app_date] => 2016-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 37 [patent_no_of_words] => 9825 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15219764 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/219764
Thin film element, semiconductor device, and method for manufacturing the same Jul 25, 2016 Issued
Array ( [id] => 11125382 [patent_doc_number] => 20160322356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 15/209662 [patent_app_country] => US [patent_app_date] => 2016-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2392 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209662 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/209662
Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods Jul 12, 2016 Issued
Array ( [id] => 11904452 [patent_doc_number] => 09773894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Application of super lattice films on insulator to lateral bipolar transistors' [patent_app_type] => utility [patent_app_number] => 15/206725 [patent_app_country] => US [patent_app_date] => 2016-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 7239 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15206725 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/206725
Application of super lattice films on insulator to lateral bipolar transistors Jul 10, 2016 Issued
Array ( [id] => 16218589 [patent_doc_number] => 10734412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Backside contact resistance reduction for semiconductor devices with metallization on both sides [patent_app_type] => utility [patent_app_number] => 16/306295 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 15346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16306295 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/306295
Backside contact resistance reduction for semiconductor devices with metallization on both sides Jun 30, 2016 Issued
Array ( [id] => 15078233 [patent_doc_number] => 10468618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Organic light-emitting diode and preparation method thereof, display substrate and display device [patent_app_type] => utility [patent_app_number] => 15/544071 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 10237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15544071 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/544071
Organic light-emitting diode and preparation method thereof, display substrate and display device Jun 30, 2016 Issued
Array ( [id] => 11111087 [patent_doc_number] => 20160308057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER' [patent_app_type] => utility [patent_app_number] => 15/191369 [patent_app_country] => US [patent_app_date] => 2016-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11756 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15191369 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/191369
Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer Jun 22, 2016 Issued
Array ( [id] => 12315000 [patent_doc_number] => 09941386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => Semiconductor device structure with fin structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 15/170294 [patent_app_country] => US [patent_app_date] => 2016-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 31 [patent_no_of_words] => 5822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170294 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/170294
Semiconductor device structure with fin structure and method for forming the same May 31, 2016 Issued
Array ( [id] => 13754867 [patent_doc_number] => 10170385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Semiconductor device and method of forming stacked vias within interconnect structure for FO-WLCSP [patent_app_type] => utility [patent_app_number] => 15/169261 [patent_app_country] => US [patent_app_date] => 2016-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 38 [patent_no_of_words] => 7379 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15169261 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/169261
Semiconductor device and method of forming stacked vias within interconnect structure for FO-WLCSP May 30, 2016 Issued
Array ( [id] => 11911362 [patent_doc_number] => 09780184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Electronic device with asymmetric gate strain' [patent_app_type] => utility [patent_app_number] => 15/165951 [patent_app_country] => US [patent_app_date] => 2016-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5114 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15165951 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/165951
Electronic device with asymmetric gate strain May 25, 2016 Issued
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