
Matthew E. Warren
Examiner (ID: 9293)
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2817, 2815 |
| Total Applications | 1867 |
| Issued Applications | 1521 |
| Pending Applications | 123 |
| Abandoned Applications | 248 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/242802
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Array
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[patent_title] => 'MULTI-LAYER GATE DIELECTRIC'
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Array
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[patent_issue_date] => 2018-03-13
[patent_title] => 'Thin film element, semiconductor device, and method for manufacturing the same'
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Array
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[patent_issue_date] => 2016-11-03
[patent_title] => 'MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS'
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[patent_app_number] => 15/209662
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/209662 | Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods | Jul 12, 2016 | Issued |
Array
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[patent_title] => 'Application of super lattice films on insulator to lateral bipolar transistors'
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Array
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[patent_issue_date] => 2019-11-05
[patent_title] => Organic light-emitting diode and preparation method thereof, display substrate and display device
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Array
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[patent_title] => Backside contact resistance reduction for semiconductor devices with metallization on both sides
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Array
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[patent_doc_number] => 20160308057
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[patent_issue_date] => 2016-10-20
[patent_title] => 'STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER'
[patent_app_type] => utility
[patent_app_number] => 15/191369
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/191369 | Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer | Jun 22, 2016 | Issued |
Array
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[patent_title] => Semiconductor device structure with fin structure and method for forming the same
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Array
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[patent_title] => Semiconductor device and method of forming stacked vias within interconnect structure for FO-WLCSP
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[patent_app_number] => 15/169261
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Array
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[patent_title] => 'Electronic device with asymmetric gate strain'
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Array
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[patent_title] => SOI MEMORY DEVICE
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/159130 | Array substrate and manufacturing method thereof, display device | May 18, 2016 | Issued |
Array
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[patent_title] => Substrate structure with array of micrometer scale copper pillar based structures and method for manufacturing same
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/157945 | Non-volatile memory device containing oxygen-scavenging material portions and method of making thereof | May 17, 2016 | Issued |