Search

Matthew E. Warren

Examiner (ID: 9293)

Most Active Art Unit
2815
Art Unit(s)
2817, 2815
Total Applications
1867
Issued Applications
1521
Pending Applications
123
Abandoned Applications
248

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11439437 [patent_doc_number] => 20170040458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/242802 [patent_app_country] => US [patent_app_date] => 2016-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 29760 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15242802 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/242802
Semiconductor device Aug 21, 2016 Issued
Array ( [id] => 11293892 [patent_doc_number] => 20160343824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'MULTI-LAYER GATE DIELECTRIC' [patent_app_type] => utility [patent_app_number] => 15/225785 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225785 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/225785
MULTI-LAYER GATE DIELECTRIC Jul 31, 2016 Abandoned
Array ( [id] => 12229948 [patent_doc_number] => 09917197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Thin film element, semiconductor device, and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 15/219764 [patent_app_country] => US [patent_app_date] => 2016-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 37 [patent_no_of_words] => 9825 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15219764 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/219764
Thin film element, semiconductor device, and method for manufacturing the same Jul 25, 2016 Issued
Array ( [id] => 11125382 [patent_doc_number] => 20160322356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 15/209662 [patent_app_country] => US [patent_app_date] => 2016-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2392 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209662 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/209662
Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods Jul 12, 2016 Issued
Array ( [id] => 11904452 [patent_doc_number] => 09773894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Application of super lattice films on insulator to lateral bipolar transistors' [patent_app_type] => utility [patent_app_number] => 15/206725 [patent_app_country] => US [patent_app_date] => 2016-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 7239 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15206725 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/206725
Application of super lattice films on insulator to lateral bipolar transistors Jul 10, 2016 Issued
Array ( [id] => 15078233 [patent_doc_number] => 10468618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Organic light-emitting diode and preparation method thereof, display substrate and display device [patent_app_type] => utility [patent_app_number] => 15/544071 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 10237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15544071 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/544071
Organic light-emitting diode and preparation method thereof, display substrate and display device Jun 30, 2016 Issued
Array ( [id] => 16218589 [patent_doc_number] => 10734412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Backside contact resistance reduction for semiconductor devices with metallization on both sides [patent_app_type] => utility [patent_app_number] => 16/306295 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 15346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16306295 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/306295
Backside contact resistance reduction for semiconductor devices with metallization on both sides Jun 30, 2016 Issued
Array ( [id] => 11111087 [patent_doc_number] => 20160308057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER' [patent_app_type] => utility [patent_app_number] => 15/191369 [patent_app_country] => US [patent_app_date] => 2016-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11756 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15191369 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/191369
Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer Jun 22, 2016 Issued
Array ( [id] => 12315000 [patent_doc_number] => 09941386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => Semiconductor device structure with fin structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 15/170294 [patent_app_country] => US [patent_app_date] => 2016-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 31 [patent_no_of_words] => 5822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170294 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/170294
Semiconductor device structure with fin structure and method for forming the same May 31, 2016 Issued
Array ( [id] => 13754867 [patent_doc_number] => 10170385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Semiconductor device and method of forming stacked vias within interconnect structure for FO-WLCSP [patent_app_type] => utility [patent_app_number] => 15/169261 [patent_app_country] => US [patent_app_date] => 2016-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 38 [patent_no_of_words] => 7379 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15169261 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/169261
Semiconductor device and method of forming stacked vias within interconnect structure for FO-WLCSP May 30, 2016 Issued
Array ( [id] => 11911362 [patent_doc_number] => 09780184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Electronic device with asymmetric gate strain' [patent_app_type] => utility [patent_app_number] => 15/165951 [patent_app_country] => US [patent_app_date] => 2016-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5114 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15165951 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/165951
Electronic device with asymmetric gate strain May 25, 2016 Issued
Array ( [id] => 12990274 [patent_doc_number] => 20170345834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => SOI MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/163785 [patent_app_country] => US [patent_app_date] => 2016-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15163785 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/163785
SOI MEMORY DEVICE May 24, 2016 Abandoned
Array ( [id] => 14205793 [patent_doc_number] => 10270025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Semiconductor structure having magnetic tunneling junction (MTJ) layer [patent_app_type] => utility [patent_app_number] => 15/159669 [patent_app_country] => US [patent_app_date] => 2016-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8053 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15159669 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/159669
Semiconductor structure having magnetic tunneling junction (MTJ) layer May 18, 2016 Issued
Array ( [id] => 12192607 [patent_doc_number] => 09896327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'CMOS-MEMS structures with out-of-plane MEMS sensing gap' [patent_app_type] => utility [patent_app_number] => 15/158947 [patent_app_country] => US [patent_app_date] => 2016-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4651 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15158947 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/158947
CMOS-MEMS structures with out-of-plane MEMS sensing gap May 18, 2016 Issued
Array ( [id] => 11386004 [patent_doc_number] => 20170012060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'Array Substrate and Manufacturing Method Thereof, Display Device' [patent_app_type] => utility [patent_app_number] => 15/159130 [patent_app_country] => US [patent_app_date] => 2016-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15159130 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/159130
Array substrate and manufacturing method thereof, display device May 18, 2016 Issued
Array ( [id] => 13228685 [patent_doc_number] => 10128123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Substrate structure with array of micrometer scale copper pillar based structures and method for manufacturing same [patent_app_type] => utility [patent_app_number] => 15/159172 [patent_app_country] => US [patent_app_date] => 2016-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 6888 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15159172 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/159172
Substrate structure with array of micrometer scale copper pillar based structures and method for manufacturing same May 18, 2016 Issued
Array ( [id] => 11293777 [patent_doc_number] => 20160343709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/159464 [patent_app_country] => US [patent_app_date] => 2016-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 60 [patent_no_of_words] => 12240 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15159464 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/159464
Semiconductor device including a semiconductor extension layer between active regions May 18, 2016 Issued
Array ( [id] => 11831798 [patent_doc_number] => 09728547 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-08 [patent_title] => 'Three-dimensional memory device with aluminum-containing etch stop layer for backside contact structure and method of making thereof' [patent_app_type] => utility [patent_app_number] => 15/159034 [patent_app_country] => US [patent_app_date] => 2016-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 38 [patent_no_of_words] => 17343 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15159034 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/159034
Three-dimensional memory device with aluminum-containing etch stop layer for backside contact structure and method of making thereof May 18, 2016 Issued
Array ( [id] => 11638171 [patent_doc_number] => 09660158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-23 [patent_title] => 'Infrared emitter' [patent_app_type] => utility [patent_app_number] => 15/159397 [patent_app_country] => US [patent_app_date] => 2016-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5403 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15159397 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/159397
Infrared emitter May 18, 2016 Issued
Array ( [id] => 12019795 [patent_doc_number] => 09812505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Non-volatile memory device containing oxygen-scavenging material portions and method of making thereof' [patent_app_type] => utility [patent_app_number] => 15/157945 [patent_app_country] => US [patent_app_date] => 2016-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 69 [patent_no_of_words] => 17061 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15157945 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/157945
Non-volatile memory device containing oxygen-scavenging material portions and method of making thereof May 17, 2016 Issued
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