Search

Matthew E. Warren

Examiner (ID: 9271, Phone: (571)272-1737 , Office: P/2815 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2817
Total Applications
1856
Issued Applications
1508
Pending Applications
127
Abandoned Applications
248

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9161535 [patent_doc_number] => 20130309812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'INTEGRATED CHIP PACKAGE STRUCTURE USING CERAMIC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/887093 [patent_app_country] => US [patent_app_date] => 2013-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6677 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13887093 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/887093
Integrated chip package structure using ceramic substrate and method of manufacturing the same May 2, 2013 Issued
Array ( [id] => 9013974 [patent_doc_number] => 20130228938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'HIGH SPEED, HIGH DENSITY, LOW POWER DIE INTERCONNECT SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/865604 [patent_app_country] => US [patent_app_date] => 2013-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 19512 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13865604 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/865604
High speed, high density, low power die interconnect system Apr 17, 2013 Issued
Array ( [id] => 9000408 [patent_doc_number] => 20130221533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'HIGH SPEED, HIGH DENSITY, LOW POWER DIE INTERCONNECT SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/865499 [patent_app_country] => US [patent_app_date] => 2013-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 19512 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13865499 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/865499
High speed, high density, low power die interconnect system Apr 17, 2013 Issued
Array ( [id] => 9003823 [patent_doc_number] => 20130224947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/862268 [patent_app_country] => US [patent_app_date] => 2013-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 19612 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13862268 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/862268
Semiconductor device and manufacturing method thereof Apr 11, 2013 Issued
Array ( [id] => 11904507 [patent_doc_number] => 09773950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Semiconductor device structure' [patent_app_type] => utility [patent_app_number] => 14/390611 [patent_app_country] => US [patent_app_date] => 2013-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 57 [patent_no_of_words] => 11310 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14390611 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/390611
Semiconductor device structure Apr 4, 2013 Issued
Array ( [id] => 11615676 [patent_doc_number] => 09653539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/777673 [patent_app_country] => US [patent_app_date] => 2013-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8228 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14777673 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/777673
Semiconductor device Mar 24, 2013 Issued
Array ( [id] => 11615535 [patent_doc_number] => 09653396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/777454 [patent_app_country] => US [patent_app_date] => 2013-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 43 [patent_no_of_words] => 37915 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14777454 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/777454
Semiconductor device and method of manufacturing the same Mar 24, 2013 Issued
Array ( [id] => 8987128 [patent_doc_number] => 20130214409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'Semiconductor Device and Method of Forming Bond-on-Lead Interconnection for Mounting Semiconductor Die in FO-WLCSP' [patent_app_type] => utility [patent_app_number] => 13/845542 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5845 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13845542 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/845542
Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in Fo-WLCSP Mar 17, 2013 Issued
Array ( [id] => 9003771 [patent_doc_number] => 20130224896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'MICRO-ELECTRO-MECHANICAL SYSTEM TILTABLE LENS' [patent_app_type] => utility [patent_app_number] => 13/842564 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10470 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13842564 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/842564
Micro-electro-mechanical system tiltable lens Mar 14, 2013 Issued
Array ( [id] => 9728241 [patent_doc_number] => 20140263947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'ENHANCED DYNAMIC RANGE IMAGING' [patent_app_type] => utility [patent_app_number] => 13/833664 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6849 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13833664 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/833664
ENHANCED DYNAMIC RANGE IMAGING Mar 14, 2013 Abandoned
Array ( [id] => 9824022 [patent_doc_number] => 08933508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Memory with isolation structure' [patent_app_type] => utility [patent_app_number] => 13/799084 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4050 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13799084 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/799084
Memory with isolation structure Mar 12, 2013 Issued
Array ( [id] => 8928045 [patent_doc_number] => 20130183805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'HIGH CAPACITANCE TRENCH CAPACITOR' [patent_app_type] => utility [patent_app_number] => 13/788980 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13788980 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/788980
High capacitance trench capacitor Mar 6, 2013 Issued
Array ( [id] => 9079152 [patent_doc_number] => 20130264682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/763798 [patent_app_country] => US [patent_app_date] => 2013-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2651 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13763798 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/763798
Transistor with heat sink joined to only part of one electrode Feb 10, 2013 Issued
Array ( [id] => 11787631 [patent_doc_number] => 09397093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Three dimensional NAND device with semiconductor, metal or silicide floating gates and method of making thereof' [patent_app_type] => utility [patent_app_number] => 13/762988 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 33 [patent_no_of_words] => 6911 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762988 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/762988
Three dimensional NAND device with semiconductor, metal or silicide floating gates and method of making thereof Feb 7, 2013 Issued
Array ( [id] => 11043722 [patent_doc_number] => 20160240678 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2016-08-18 [patent_title] => 'STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER' [patent_app_type] => utility [patent_app_number] => 13/762677 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11736 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762677 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/762677
Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer Feb 7, 2013 Issued
Array ( [id] => 9654214 [patent_doc_number] => 20140225219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'FinFETs with Reduced Parasitic Capacitance and Methods of Forming the Same' [patent_app_type] => utility [patent_app_number] => 13/763242 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13763242 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/763242
FinFETs with reduced parasitic capacitance and methods of forming the same Feb 7, 2013 Issued
Array ( [id] => 11043722 [patent_doc_number] => 20160240678 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2016-08-18 [patent_title] => 'STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER' [patent_app_type] => utility [patent_app_number] => 13/762677 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11736 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762677 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/762677
Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer Feb 7, 2013 Issued
Array ( [id] => 8974206 [patent_doc_number] => 20130207636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'REFERENCE VOLTAGE GENERATOR' [patent_app_type] => utility [patent_app_number] => 13/755545 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2588 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755545 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/755545
Reference voltage generator Jan 30, 2013 Issued
Array ( [id] => 13819413 [patent_doc_number] => 10186480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same [patent_app_type] => utility [patent_app_number] => 13/741382 [patent_app_country] => US [patent_app_date] => 2013-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13741382 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/741382
Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same Jan 13, 2013 Issued
Array ( [id] => 9482981 [patent_doc_number] => 08728932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Contact for memory cell' [patent_app_type] => utility [patent_app_number] => 13/734476 [patent_app_country] => US [patent_app_date] => 2013-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3913 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13734476 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/734476
Contact for memory cell Jan 3, 2013 Issued
Menu