
Matthew E. Warren
Examiner (ID: 9293)
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2817, 2815 |
| Total Applications | 1867 |
| Issued Applications | 1521 |
| Pending Applications | 123 |
| Abandoned Applications | 248 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9728241
[patent_doc_number] => 20140263947
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'ENHANCED DYNAMIC RANGE IMAGING'
[patent_app_type] => utility
[patent_app_number] => 13/833664
[patent_app_country] => US
[patent_app_date] => 2013-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6849
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13833664
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/833664 | ENHANCED DYNAMIC RANGE IMAGING | Mar 14, 2013 | Abandoned |
Array
(
[id] => 9824022
[patent_doc_number] => 08933508
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-13
[patent_title] => 'Memory with isolation structure'
[patent_app_type] => utility
[patent_app_number] => 13/799084
[patent_app_country] => US
[patent_app_date] => 2013-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4050
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13799084
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/799084 | Memory with isolation structure | Mar 12, 2013 | Issued |
Array
(
[id] => 8928045
[patent_doc_number] => 20130183805
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-18
[patent_title] => 'HIGH CAPACITANCE TRENCH CAPACITOR'
[patent_app_type] => utility
[patent_app_number] => 13/788980
[patent_app_country] => US
[patent_app_date] => 2013-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 10361
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13788980
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/788980 | High capacitance trench capacitor | Mar 6, 2013 | Issued |
Array
(
[id] => 9079152
[patent_doc_number] => 20130264682
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-10
[patent_title] => 'TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 13/763798
[patent_app_country] => US
[patent_app_date] => 2013-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2651
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13763798
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/763798 | Transistor with heat sink joined to only part of one electrode | Feb 10, 2013 | Issued |
Array
(
[id] => 11043722
[patent_doc_number] => 20160240678
[patent_country] => US
[patent_kind] => A9
[patent_issue_date] => 2016-08-18
[patent_title] => 'STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER'
[patent_app_type] => utility
[patent_app_number] => 13/762677
[patent_app_country] => US
[patent_app_date] => 2013-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 11736
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762677
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/762677 | Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer | Feb 7, 2013 | Issued |
Array
(
[id] => 11043722
[patent_doc_number] => 20160240678
[patent_country] => US
[patent_kind] => A9
[patent_issue_date] => 2016-08-18
[patent_title] => 'STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER'
[patent_app_type] => utility
[patent_app_number] => 13/762677
[patent_app_country] => US
[patent_app_date] => 2013-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 11736
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762677
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/762677 | Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer | Feb 7, 2013 | Issued |
Array
(
[id] => 9654214
[patent_doc_number] => 20140225219
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-14
[patent_title] => 'FinFETs with Reduced Parasitic Capacitance and Methods of Forming the Same'
[patent_app_type] => utility
[patent_app_number] => 13/763242
[patent_app_country] => US
[patent_app_date] => 2013-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 3661
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13763242
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/763242 | FinFETs with reduced parasitic capacitance and methods of forming the same | Feb 7, 2013 | Issued |
Array
(
[id] => 11787631
[patent_doc_number] => 09397093
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-07-19
[patent_title] => 'Three dimensional NAND device with semiconductor, metal or silicide floating gates and method of making thereof'
[patent_app_type] => utility
[patent_app_number] => 13/762988
[patent_app_country] => US
[patent_app_date] => 2013-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 33
[patent_no_of_words] => 6911
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762988
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/762988 | Three dimensional NAND device with semiconductor, metal or silicide floating gates and method of making thereof | Feb 7, 2013 | Issued |
Array
(
[id] => 8974206
[patent_doc_number] => 20130207636
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-15
[patent_title] => 'REFERENCE VOLTAGE GENERATOR'
[patent_app_type] => utility
[patent_app_number] => 13/755545
[patent_app_country] => US
[patent_app_date] => 2013-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2588
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755545
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/755545 | Reference voltage generator | Jan 30, 2013 | Issued |
Array
(
[id] => 13819413
[patent_doc_number] => 10186480
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-22
[patent_title] => Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
[patent_app_type] => utility
[patent_app_number] => 13/741382
[patent_app_country] => US
[patent_app_date] => 2013-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 6003
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13741382
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/741382 | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same | Jan 13, 2013 | Issued |
Array
(
[id] => 9482981
[patent_doc_number] => 08728932
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-20
[patent_title] => 'Contact for memory cell'
[patent_app_type] => utility
[patent_app_number] => 13/734476
[patent_app_country] => US
[patent_app_date] => 2013-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 3913
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13734476
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/734476 | Contact for memory cell | Jan 3, 2013 | Issued |
Array
(
[id] => 8838921
[patent_doc_number] => 20130134549
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-30
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/725389
[patent_app_country] => US
[patent_app_date] => 2012-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 6621
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13725389
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/725389 | Semiconductor device and method for manufacturing the same | Dec 20, 2012 | Issued |
Array
(
[id] => 8956563
[patent_doc_number] => 08502342
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-08-06
[patent_title] => 'Circuits, systems, and methods for reducing effects of cross talk in I/O lines and wire bonds'
[patent_app_type] => utility
[patent_app_number] => 13/684331
[patent_app_country] => US
[patent_app_date] => 2012-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 7312
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13684331
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/684331 | Circuits, systems, and methods for reducing effects of cross talk in I/O lines and wire bonds | Nov 22, 2012 | Issued |
Array
(
[id] => 10858131
[patent_doc_number] => 08884335
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-11
[patent_title] => 'Semiconductor including lateral HEMT'
[patent_app_type] => utility
[patent_app_number] => 13/681958
[patent_app_country] => US
[patent_app_date] => 2012-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 22
[patent_no_of_words] => 6972
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13681958
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/681958 | Semiconductor including lateral HEMT | Nov 19, 2012 | Issued |
Array
(
[id] => 9171707
[patent_doc_number] => 20130313692
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-28
[patent_title] => 'ANTENNA IN PACKAGE WITH REDUCED ELECTROMAGNETIC INTERACTION WITH ON CHIP ELEMENTS'
[patent_app_type] => utility
[patent_app_number] => 13/673750
[patent_app_country] => US
[patent_app_date] => 2012-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 6924
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13673750
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/673750 | ANTENNA IN PACKAGE WITH REDUCED ELECTROMAGNETIC INTERACTION WITH ON CHIP ELEMENTS | Nov 8, 2012 | Abandoned |
Array
(
[id] => 10525218
[patent_doc_number] => 09251734
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-02
[patent_title] => 'Pixel circuit, electro-optical device, and electronic apparatus'
[patent_app_type] => utility
[patent_app_number] => 13/669002
[patent_app_country] => US
[patent_app_date] => 2012-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 23
[patent_no_of_words] => 16552
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 240
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13669002
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/669002 | Pixel circuit, electro-optical device, and electronic apparatus | Nov 4, 2012 | Issued |
Array
(
[id] => 8659599
[patent_doc_number] => 20130040428
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-14
[patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/653068
[patent_app_country] => US
[patent_app_date] => 2012-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 5382
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13653068
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/653068 | Semiconductor package and method of fabricating the same | Oct 15, 2012 | Issued |
Array
(
[id] => 8697411
[patent_doc_number] => 20130059421
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-07
[patent_title] => 'METHOD FOR RADIATION HARDENING AN INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 13/629369
[patent_app_country] => US
[patent_app_date] => 2012-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9954
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13629369
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/629369 | METHOD FOR RADIATION HARDENING AN INTEGRATED CIRCUIT | Sep 26, 2012 | Abandoned |
Array
(
[id] => 11301107
[patent_doc_number] => 09509122
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-11-29
[patent_title] => 'Optical cladding layer design'
[patent_app_type] => utility
[patent_app_number] => 13/597701
[patent_app_country] => US
[patent_app_date] => 2012-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3613
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13597701
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/597701 | Optical cladding layer design | Aug 28, 2012 | Issued |
Array
(
[id] => 10145170
[patent_doc_number] => 09177986
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-11-03
[patent_title] => 'Isolation for semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 13/598275
[patent_app_country] => US
[patent_app_date] => 2012-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5883
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13598275
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/598275 | Isolation for semiconductor devices | Aug 28, 2012 | Issued |