
Matthew E. Warren
Examiner (ID: 9271, Phone: (571)272-1737 , Office: P/2815 )
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815, 2817 |
| Total Applications | 1856 |
| Issued Applications | 1508 |
| Pending Applications | 127 |
| Abandoned Applications | 248 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5932501
[patent_doc_number] => 20110210425
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-01
[patent_title] => 'FORMATION OF GROUP III-V MATERIAL LAYERS ON PATTERNED SUBSTRATES'
[patent_app_type] => utility
[patent_app_number] => 13/036261
[patent_app_country] => US
[patent_app_date] => 2011-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5215
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0210/20110210425.pdf
[firstpage_image] =>[orig_patent_app_number] => 13036261
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/036261 | Formation of group III-V material layers on patterned substrates | Feb 27, 2011 | Issued |
Array
(
[id] => 7654758
[patent_doc_number] => 20110304027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-15
[patent_title] => 'SEMICONDUCTOR CHIP WITH THROUGH ELECTRODES AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/036372
[patent_app_country] => US
[patent_app_date] => 2011-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 5955
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0304/20110304027.pdf
[firstpage_image] =>[orig_patent_app_number] => 13036372
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/036372 | SEMICONDUCTOR CHIP WITH THROUGH ELECTRODES AND METHOD FOR MANUFACTURING THE SAME | Feb 27, 2011 | Abandoned |
Array
(
[id] => 10850957
[patent_doc_number] => 08877636
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-11-04
[patent_title] => 'Processing of nanostructured devices using microfabrication techniques'
[patent_app_type] => utility
[patent_app_number] => 13/036887
[patent_app_country] => US
[patent_app_date] => 2011-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
[patent_figures_cnt] => 38
[patent_no_of_words] => 19843
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13036887
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/036887 | Processing of nanostructured devices using microfabrication techniques | Feb 27, 2011 | Issued |
Array
(
[id] => 7699511
[patent_doc_number] => 20110227079
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-22
[patent_title] => 'THIN FILM TRANSISTOR, DISPLAY DEVICE THEREOF, AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/036241
[patent_app_country] => US
[patent_app_date] => 2011-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 7410
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0227/20110227079.pdf
[firstpage_image] =>[orig_patent_app_number] => 13036241
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/036241 | Thin film transistor, display device thereof, and manufacturing method thereof | Feb 27, 2011 | Issued |
Array
(
[id] => 10844402
[patent_doc_number] => 08871576
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-28
[patent_title] => 'Silicon nanotube MOSFET'
[patent_app_type] => utility
[patent_app_number] => 13/036292
[patent_app_country] => US
[patent_app_date] => 2011-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 22
[patent_no_of_words] => 3924
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13036292
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/036292 | Silicon nanotube MOSFET | Feb 27, 2011 | Issued |
Array
(
[id] => 7805245
[patent_doc_number] => 20120056197
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-08
[patent_title] => 'SEMICONDUCTOR RECTIFYING DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/036940
[patent_app_country] => US
[patent_app_date] => 2011-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 12122
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0056/20120056197.pdf
[firstpage_image] =>[orig_patent_app_number] => 13036940
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/036940 | Semiconductor rectifying device | Feb 27, 2011 | Issued |
Array
(
[id] => 8368216
[patent_doc_number] => 20120217610
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-30
[patent_title] => 'Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openings and Projections'
[patent_app_type] => utility
[patent_app_number] => 13/037281
[patent_app_country] => US
[patent_app_date] => 2011-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 5755
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13037281
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/037281 | Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openings and Projections | Feb 27, 2011 | Abandoned |
Array
(
[id] => 8368173
[patent_doc_number] => 20120217561
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-30
[patent_title] => 'Structure And Method For Adjusting Threshold Voltage Of The Array Of Transistors'
[patent_app_type] => utility
[patent_app_number] => 13/036243
[patent_app_country] => US
[patent_app_date] => 2011-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 16138
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13036243
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/036243 | Structure and method for adjusting threshold voltage of the array of transistors | Feb 27, 2011 | Issued |
Array
(
[id] => 5932234
[patent_doc_number] => 20110210339
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-01
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/034278
[patent_app_country] => US
[patent_app_date] => 2011-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 19879
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0210/20110210339.pdf
[firstpage_image] =>[orig_patent_app_number] => 13034278
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/034278 | Semiconductor device including a memory cell | Feb 23, 2011 | Issued |
Array
(
[id] => 9832413
[patent_doc_number] => 08941232
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-27
[patent_title] => 'Metal bumps for cooling device connection'
[patent_app_type] => utility
[patent_app_number] => 13/034263
[patent_app_country] => US
[patent_app_date] => 2011-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 22
[patent_no_of_words] => 4877
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13034263
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/034263 | Metal bumps for cooling device connection | Feb 23, 2011 | Issued |
Array
(
[id] => 6208346
[patent_doc_number] => 20110133270
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-09
[patent_title] => 'MEMORY DEVICE WITH RECESSED CONSTRUCTION BETWEEN MEMORY CONSTRUCTIONS'
[patent_app_type] => utility
[patent_app_number] => 13/025047
[patent_app_country] => US
[patent_app_date] => 2011-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4014
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20110133270.pdf
[firstpage_image] =>[orig_patent_app_number] => 13025047
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/025047 | Memory device with recessed construction between memory constructions | Feb 9, 2011 | Issued |
Array
(
[id] => 6208346
[patent_doc_number] => 20110133270
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-09
[patent_title] => 'MEMORY DEVICE WITH RECESSED CONSTRUCTION BETWEEN MEMORY CONSTRUCTIONS'
[patent_app_type] => utility
[patent_app_number] => 13/025047
[patent_app_country] => US
[patent_app_date] => 2011-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4014
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20110133270.pdf
[firstpage_image] =>[orig_patent_app_number] => 13025047
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/025047 | Memory device with recessed construction between memory constructions | Feb 9, 2011 | Issued |
Array
(
[id] => 6208346
[patent_doc_number] => 20110133270
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-09
[patent_title] => 'MEMORY DEVICE WITH RECESSED CONSTRUCTION BETWEEN MEMORY CONSTRUCTIONS'
[patent_app_type] => utility
[patent_app_number] => 13/025047
[patent_app_country] => US
[patent_app_date] => 2011-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4014
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20110133270.pdf
[firstpage_image] =>[orig_patent_app_number] => 13025047
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/025047 | Memory device with recessed construction between memory constructions | Feb 9, 2011 | Issued |
Array
(
[id] => 6208346
[patent_doc_number] => 20110133270
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-09
[patent_title] => 'MEMORY DEVICE WITH RECESSED CONSTRUCTION BETWEEN MEMORY CONSTRUCTIONS'
[patent_app_type] => utility
[patent_app_number] => 13/025047
[patent_app_country] => US
[patent_app_date] => 2011-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4014
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20110133270.pdf
[firstpage_image] =>[orig_patent_app_number] => 13025047
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/025047 | Memory device with recessed construction between memory constructions | Feb 9, 2011 | Issued |
Array
(
[id] => 7660145
[patent_doc_number] => 20110309414
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-22
[patent_title] => 'Diode polarity for diode array'
[patent_app_type] => utility
[patent_app_number] => 12/930655
[patent_app_country] => US
[patent_app_date] => 2011-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3294
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0309/20110309414.pdf
[firstpage_image] =>[orig_patent_app_number] => 12930655
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/930655 | Diode polarity for diode array | Jan 12, 2011 | Abandoned |
Array
(
[id] => 8933067
[patent_doc_number] => 08492769
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-23
[patent_title] => 'Transistor including multi-layer reentrant profile'
[patent_app_type] => utility
[patent_app_number] => 12/986241
[patent_app_country] => US
[patent_app_date] => 2011-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 6268
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12986241
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/986241 | Transistor including multi-layer reentrant profile | Jan 6, 2011 | Issued |
Array
(
[id] => 8287341
[patent_doc_number] => 20120175672
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-12
[patent_title] => 'ESD PROTECTION CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/986970
[patent_app_country] => US
[patent_app_date] => 2011-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4058
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12986970
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/986970 | ESD protection circuit | Jan 6, 2011 | Issued |
Array
(
[id] => 7479795
[patent_doc_number] => 20110248258
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-10-13
[patent_title] => 'ORGANIC-LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/985931
[patent_app_country] => US
[patent_app_date] => 2011-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4947
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0248/20110248258.pdf
[firstpage_image] =>[orig_patent_app_number] => 12985931
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/985931 | Organic-light emitting device and method of manufacturing the same | Jan 5, 2011 | Issued |
Array
(
[id] => 8287397
[patent_doc_number] => 20120175724
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-12
[patent_title] => 'Trenched Schottky Diode and Method of Forming a Trenched Schottky Diode'
[patent_app_type] => utility
[patent_app_number] => 12/986107
[patent_app_country] => US
[patent_app_date] => 2011-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 3391
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12986107
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/986107 | Trenched Schottky diode and method of forming a trenched Schottky diode | Jan 5, 2011 | Issued |
Array
(
[id] => 9239094
[patent_doc_number] => 08603885
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-12-10
[patent_title] => 'Flat response device structures for bipolar junction transistors'
[patent_app_type] => utility
[patent_app_number] => 12/984359
[patent_app_country] => US
[patent_app_date] => 2011-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 7762
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12984359
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/984359 | Flat response device structures for bipolar junction transistors | Jan 3, 2011 | Issued |