
Matthew E. Warren
Examiner (ID: 9271, Phone: (571)272-1737 , Office: P/2815 )
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815, 2817 |
| Total Applications | 1856 |
| Issued Applications | 1508 |
| Pending Applications | 127 |
| Abandoned Applications | 248 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5177574
[patent_doc_number] => 20070178634
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-02
[patent_title] => 'CMOS SEMICONDUCTOR DEVICES HAVING DUAL WORK FUNCTION METAL GATE STACKS'
[patent_app_type] => utility
[patent_app_number] => 11/550602
[patent_app_country] => US
[patent_app_date] => 2006-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5683
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0178/20070178634.pdf
[firstpage_image] =>[orig_patent_app_number] => 11550602
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/550602 | CMOS SEMICONDUCTOR DEVICES HAVING DUAL WORK FUNCTION METAL GATE STACKS | Oct 17, 2006 | Abandoned |
Array
(
[id] => 5120080
[patent_doc_number] => 20070141794
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-21
[patent_title] => 'Radiation hardened isolation structures and fabrication methods'
[patent_app_type] => utility
[patent_app_number] => 11/581561
[patent_app_country] => US
[patent_app_date] => 2006-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9904
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20070141794.pdf
[firstpage_image] =>[orig_patent_app_number] => 11581561
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/581561 | Radiation hardened isolation structures and fabrication methods | Oct 15, 2006 | Issued |
Array
(
[id] => 5217388
[patent_doc_number] => 20070158699
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-12
[patent_title] => 'SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 11/538631
[patent_app_country] => US
[patent_app_date] => 2006-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 9899
[patent_no_of_claims] => 34
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20070158699.pdf
[firstpage_image] =>[orig_patent_app_number] => 11538631
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/538631 | Semiconductor device and semiconductor system | Oct 3, 2006 | Issued |
Array
(
[id] => 5219815
[patent_doc_number] => 20070161126
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-12
[patent_title] => 'Ferroelectric capacitor and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/540752
[patent_app_country] => US
[patent_app_date] => 2006-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7052
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20070161126.pdf
[firstpage_image] =>[orig_patent_app_number] => 11540752
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/540752 | Ferroelectric capacitor and method for fabricating the same | Oct 1, 2006 | Abandoned |
Array
(
[id] => 5253396
[patent_doc_number] => 20070134852
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-14
[patent_title] => 'Layout method of power line for semiconductor integrated circuit and semiconductor integrated circuit manufactured by the layout method'
[patent_app_type] => utility
[patent_app_number] => 11/523212
[patent_app_country] => US
[patent_app_date] => 2006-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3150
[patent_no_of_claims] => 8
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0134/20070134852.pdf
[firstpage_image] =>[orig_patent_app_number] => 11523212
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/523212 | Layout method of power line for semiconductor integrated circuit and semiconductor integrated circuit manufactured by the layout method | Sep 18, 2006 | Issued |
Array
(
[id] => 5257185
[patent_doc_number] => 20070210817
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-13
[patent_title] => 'Partitioned multi-die wafer-sort probe card and methods of using same'
[patent_app_type] => utility
[patent_app_number] => 11/521912
[patent_app_country] => US
[patent_app_date] => 2006-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 5759
[patent_no_of_claims] => 26
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0210/20070210817.pdf
[firstpage_image] =>[orig_patent_app_number] => 11521912
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/521912 | Partitioned multi-die wafer-sort probe card and methods of using same | Sep 14, 2006 | Abandoned |
Array
(
[id] => 5104417
[patent_doc_number] => 20070063292
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-22
[patent_title] => 'Semiconductor apparatus integrating an electrical device under an electrode pad'
[patent_app_type] => utility
[patent_app_number] => 11/517781
[patent_app_country] => US
[patent_app_date] => 2006-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 8938
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0063/20070063292.pdf
[firstpage_image] =>[orig_patent_app_number] => 11517781
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/517781 | Semiconductor apparatus integrating an electrical device under an electrode pad | Sep 7, 2006 | Issued |
Array
(
[id] => 5077040
[patent_doc_number] => 20070120264
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-31
[patent_title] => 'A SEMICONDUCTOR HAVING A COPPER-BASED METALLIZATION STACK WITH A LAST ALUMINUM METAL LINE LAYER'
[patent_app_type] => utility
[patent_app_number] => 11/530071
[patent_app_country] => US
[patent_app_date] => 2006-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6596
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20070120264.pdf
[firstpage_image] =>[orig_patent_app_number] => 11530071
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/530071 | A SEMICONDUCTOR HAVING A COPPER-BASED METALLIZATION STACK WITH A LAST ALUMINUM METAL LINE LAYER | Sep 7, 2006 | Abandoned |
Array
(
[id] => 4772019
[patent_doc_number] => 20080057677
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-06
[patent_title] => 'CHIP LOCATION IDENTIFICATION'
[patent_app_type] => utility
[patent_app_number] => 11/470355
[patent_app_country] => US
[patent_app_date] => 2006-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1804
[patent_no_of_claims] => 9
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20080057677.pdf
[firstpage_image] =>[orig_patent_app_number] => 11470355
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/470355 | CHIP LOCATION IDENTIFICATION | Sep 5, 2006 | Abandoned |
Array
(
[id] => 5139024
[patent_doc_number] => 20070001240
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-04
[patent_title] => 'Seal ring for mixed circuitry semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 11/515172
[patent_app_country] => US
[patent_app_date] => 2006-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3291
[patent_no_of_claims] => 13
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20070001240.pdf
[firstpage_image] =>[orig_patent_app_number] => 11515172
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/515172 | Seal ring for mixed circuitry semiconductor devices | Aug 30, 2006 | Issued |
Array
(
[id] => 5157479
[patent_doc_number] => 20070170523
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-26
[patent_title] => 'CIRCUIT SUBSTRATE AND PACKAGING THEREOF AND THE METHOD FOR FABRICATING THE PACKAGING'
[patent_app_type] => utility
[patent_app_number] => 11/468341
[patent_app_country] => US
[patent_app_date] => 2006-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 2860
[patent_no_of_claims] => 28
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0170/20070170523.pdf
[firstpage_image] =>[orig_patent_app_number] => 11468341
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/468341 | CIRCUIT SUBSTRATE AND PACKAGING THEREOF AND THE METHOD FOR FABRICATING THE PACKAGING | Aug 29, 2006 | Abandoned |
Array
(
[id] => 5145719
[patent_doc_number] => 20070045773
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-01
[patent_title] => 'Integrated electronic device and method of making the same'
[patent_app_type] => utility
[patent_app_number] => 11/509577
[patent_app_country] => US
[patent_app_date] => 2006-08-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0045/20070045773.pdf
[firstpage_image] =>[orig_patent_app_number] => 11509577
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/509577 | Integrated electronic device and method of making the same | Aug 24, 2006 | Issued |
Array
(
[id] => 5186141
[patent_doc_number] => 20070164448
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-19
[patent_title] => 'Semiconductor chip package with attached electronic devices, and integrated circuit module having the same'
[patent_app_type] => utility
[patent_app_number] => 11/505361
[patent_app_country] => US
[patent_app_date] => 2006-08-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0164/20070164448.pdf
[firstpage_image] =>[orig_patent_app_number] => 11505361
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/505361 | Semiconductor chip package with attached electronic devices, and integrated circuit module having the same | Aug 16, 2006 | Abandoned |
Array
(
[id] => 205393
[patent_doc_number] => 07629694
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-08
[patent_title] => 'Interconnections for crosswire arrays'
[patent_app_type] => utility
[patent_app_number] => 11/465101
[patent_app_country] => US
[patent_app_date] => 2006-08-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/629/07629694.pdf
[firstpage_image] =>[orig_patent_app_number] => 11465101
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/465101 | Interconnections for crosswire arrays | Aug 15, 2006 | Issued |
Array
(
[id] => 5202416
[patent_doc_number] => 20070023895
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-01
[patent_title] => 'Semiconductor device having capacitors for reducing power source noise'
[patent_app_type] => utility
[patent_app_number] => 11/501849
[patent_app_country] => US
[patent_app_date] => 2006-08-10
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11501849
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/501849 | Semiconductor device having capacitors for reducing power source noise | Aug 9, 2006 | Abandoned |
Array
(
[id] => 5605700
[patent_doc_number] => 20060267216
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-30
[patent_title] => 'INDUCTIVE FILTERS AND METHODS OF FABRICATION THEREFOR'
[patent_app_type] => utility
[patent_app_number] => 11/462611
[patent_app_country] => US
[patent_app_date] => 2006-08-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0267/20060267216.pdf
[firstpage_image] =>[orig_patent_app_number] => 11462611
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/462611 | Inductive filters and methods of fabrication therefor | Aug 3, 2006 | Issued |
Array
(
[id] => 5622983
[patent_doc_number] => 20060261488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-23
[patent_title] => 'Wafer level electro-optical simiconductor manufacture fabrication mechanism and a method for the same'
[patent_app_type] => utility
[patent_app_number] => 11/492816
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/492816 | Wafer level electro-optical simiconductor manufacture fabrication mechanism and a method for the same | Jul 25, 2006 | Abandoned |
Array
(
[id] => 4619662
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[patent_issue_date] => 2011-08-16
[patent_title] => 'High speed, high density, low power die interconnect system'
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[firstpage_image] =>[orig_patent_app_number] => 11459081
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/459081 | High speed, high density, low power die interconnect system | Jul 20, 2006 | Issued |
Array
(
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[patent_issue_date] => 2010-05-11
[patent_title] => 'Pad structure design with reduced density'
[patent_app_type] => utility
[patent_app_number] => 11/458501
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[firstpage_image] =>[orig_patent_app_number] => 11458501
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/458501 | Pad structure design with reduced density | Jul 18, 2006 | Issued |
Array
(
[id] => 574147
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[patent_title] => 'Semiconductor devices having torsional stresses'
[patent_app_type] => utility
[patent_app_number] => 11/458461
[patent_app_country] => US
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[pdf_file] => patents/07/462/07462916.pdf
[firstpage_image] =>[orig_patent_app_number] => 11458461
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/458461 | Semiconductor devices having torsional stresses | Jul 18, 2006 | Issued |