
Matthew E. Warren
Examiner (ID: 9271, Phone: (571)272-1737 , Office: P/2815 )
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815, 2817 |
| Total Applications | 1856 |
| Issued Applications | 1508 |
| Pending Applications | 127 |
| Abandoned Applications | 248 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5765504
[patent_doc_number] => 20060018355
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-26
[patent_title] => 'Laser diode arrays with reduced heat induced strain and stress'
[patent_app_type] => utility
[patent_app_number] => 10/897560
[patent_app_country] => US
[patent_app_date] => 2004-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5839
[patent_no_of_claims] => 125
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20060018355.pdf
[firstpage_image] =>[orig_patent_app_number] => 10897560
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/897560 | Laser diode arrays with reduced heat induced strain and stress | Jul 22, 2004 | Abandoned |
Array
(
[id] => 4992212
[patent_doc_number] => 20070007556
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-11
[patent_title] => 'Backside-illuminated photodetector'
[patent_app_type] => utility
[patent_app_number] => 10/565282
[patent_app_country] => US
[patent_app_date] => 2004-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 8833
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[pdf_file] => publications/A1/0007/20070007556.pdf
[firstpage_image] =>[orig_patent_app_number] => 10565282
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/565282 | Backside-illuminated photodetector | Jul 21, 2004 | Issued |
Array
(
[id] => 7404056
[patent_doc_number] => 20040262598
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-30
[patent_title] => 'Logic apparatus and logic circuit'
[patent_app_type] => new
[patent_app_number] => 10/893916
[patent_app_country] => US
[patent_app_date] => 2004-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6648
[patent_no_of_claims] => 4
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0262/20040262598.pdf
[firstpage_image] =>[orig_patent_app_number] => 10893916
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/893916 | Logic apparatus and logic circuit | Jul 19, 2004 | Issued |
Array
(
[id] => 322949
[patent_doc_number] => 07518182
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-14
[patent_title] => 'DRAM layout with vertical FETs and method of formation'
[patent_app_type] => utility
[patent_app_number] => 10/894125
[patent_app_country] => US
[patent_app_date] => 2004-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 38
[patent_no_of_words] => 10223
[patent_no_of_claims] => 21
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/518/07518182.pdf
[firstpage_image] =>[orig_patent_app_number] => 10894125
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/894125 | DRAM layout with vertical FETs and method of formation | Jul 19, 2004 | Issued |
Array
(
[id] => 7082075
[patent_doc_number] => 20050047455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-03
[patent_title] => 'Laser diode module'
[patent_app_type] => utility
[patent_app_number] => 10/891193
[patent_app_country] => US
[patent_app_date] => 2004-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4533
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0047/20050047455.pdf
[firstpage_image] =>[orig_patent_app_number] => 10891193
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/891193 | Laser diode module | Jul 14, 2004 | Abandoned |
Array
(
[id] => 616798
[patent_doc_number] => 07145211
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-05
[patent_title] => 'Seal ring for mixed circuitry semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 10/889671
[patent_app_country] => US
[patent_app_date] => 2004-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3292
[patent_no_of_claims] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/145/07145211.pdf
[firstpage_image] =>[orig_patent_app_number] => 10889671
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/889671 | Seal ring for mixed circuitry semiconductor devices | Jul 12, 2004 | Issued |
Array
(
[id] => 7058948
[patent_doc_number] => 20050001307
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => '[WAFER LEVEL PASSIVE COMPONENT]'
[patent_app_type] => utility
[patent_app_number] => 10/710301
[patent_app_country] => US
[patent_app_date] => 2004-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1622
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20050001307.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710301
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710301 | [WAFER LEVEL PASSIVE COMPONENT] | Jun 30, 2004 | Abandoned |
Array
(
[id] => 7080589
[patent_doc_number] => 20050045969
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-03
[patent_title] => 'Silicide/semiconductor structure and method of fabrication'
[patent_app_type] => utility
[patent_app_number] => 10/880992
[patent_app_country] => US
[patent_app_date] => 2004-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4277
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0045/20050045969.pdf
[firstpage_image] =>[orig_patent_app_number] => 10880992
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/880992 | Silicide/semiconductor structure and method of fabrication | Jun 29, 2004 | Issued |
Array
(
[id] => 1021515
[patent_doc_number] => 06887774
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-03
[patent_title] => 'Conductor layer nitridation'
[patent_app_type] => utility
[patent_app_number] => 10/881630
[patent_app_country] => US
[patent_app_date] => 2004-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2371
[patent_no_of_claims] => 114
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/887/06887774.pdf
[firstpage_image] =>[orig_patent_app_number] => 10881630
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/881630 | Conductor layer nitridation | Jun 29, 2004 | Issued |
Array
(
[id] => 7338691
[patent_doc_number] => 20040245645
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-09
[patent_title] => 'Semiconductor integrated circuit device having multilevel interconnection'
[patent_app_type] => new
[patent_app_number] => 10/872482
[patent_app_country] => US
[patent_app_date] => 2004-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4284
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 3
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0245/20040245645.pdf
[firstpage_image] =>[orig_patent_app_number] => 10872482
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/872482 | Semiconductor integrated circuit device having multilevel interconnection | Jun 21, 2004 | Abandoned |
Array
(
[id] => 7101489
[patent_doc_number] => 20050104215
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-19
[patent_title] => 'Barrier layers for tin-bearing solder joints'
[patent_app_type] => utility
[patent_app_number] => 10/710042
[patent_app_country] => US
[patent_app_date] => 2004-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2212
[patent_no_of_claims] => 19
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0104/20050104215.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710042
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710042 | Barrier layers for tin-bearing solder joints | Jun 14, 2004 | Abandoned |
Array
(
[id] => 260405
[patent_doc_number] => 07573133
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-11
[patent_title] => 'Interconnect structures and methods for their fabrication'
[patent_app_type] => utility
[patent_app_number] => 10/858191
[patent_app_country] => US
[patent_app_date] => 2004-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/573/07573133.pdf
[firstpage_image] =>[orig_patent_app_number] => 10858191
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/858191 | Interconnect structures and methods for their fabrication | May 31, 2004 | Issued |
Array
(
[id] => 7016500
[patent_doc_number] => 20050218517
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-06
[patent_title] => 'Semiconductor flip-chip package and method for the fabrication thereof'
[patent_app_type] => utility
[patent_app_number] => 10/855708
[patent_app_country] => US
[patent_app_date] => 2004-05-28
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0218/20050218517.pdf
[firstpage_image] =>[orig_patent_app_number] => 10855708
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/855708 | Semiconductor flip-chip package and method for the fabrication thereof | May 27, 2004 | Abandoned |
Array
(
[id] => 7291821
[patent_doc_number] => 20040212062
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Tape stiffener and semiconductor device component assemblies including same'
[patent_app_type] => new
[patent_app_number] => 10/852279
[patent_app_country] => US
[patent_app_date] => 2004-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20040212062.pdf
[firstpage_image] =>[orig_patent_app_number] => 10852279
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/852279 | Tape stiffener and semiconductor device component assemblies including same | May 23, 2004 | Abandoned |
Array
(
[id] => 7067005
[patent_doc_number] => 20050242387
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-03
[patent_title] => 'Flash memory device having a graded composition, high dielectric constant gate insulator'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2004-04-29
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0242/20050242387.pdf
[firstpage_image] =>[orig_patent_app_number] => 10835221
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/835221 | Flash memory device having a graded composition, high dielectric constant gate insulator | Apr 28, 2004 | Abandoned |
Array
(
[id] => 7604992
[patent_doc_number] => 07115938
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-03
[patent_title] => 'Non-volatile memory cell and method of forming the same'
[patent_app_type] => utility
[patent_app_number] => 10/828231
[patent_app_country] => US
[patent_app_date] => 2004-04-21
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/115/07115938.pdf
[firstpage_image] =>[orig_patent_app_number] => 10828231
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/828231 | Non-volatile memory cell and method of forming the same | Apr 20, 2004 | Issued |
Array
(
[id] => 6949788
[patent_doc_number] => 20050224882
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-13
[patent_title] => 'LOW TRIGGER VOLTAGE ESD NMOSFET TRIPLE-WELL CMOS DEVICES'
[patent_app_type] => utility
[patent_app_number] => 10/709041
[patent_app_country] => US
[patent_app_date] => 2004-04-08
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0224/20050224882.pdf
[firstpage_image] =>[orig_patent_app_number] => 10709041
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/709041 | LOW TRIGGER VOLTAGE ESD NMOSFET TRIPLE-WELL CMOS DEVICES | Apr 7, 2004 | Abandoned |
Array
(
[id] => 7403939
[patent_doc_number] => 20040175586
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-09
[patent_title] => 'Conformal thin films over textured capacitor electrodes'
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[patent_app_number] => 10/795696
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[patent_app_date] => 2004-03-03
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[pdf_file] => publications/A1/0175/20040175586.pdf
[firstpage_image] =>[orig_patent_app_number] => 10795696
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/795696 | Conformal thin films over textured capacitor electrodes | Mar 2, 2004 | Abandoned |
Array
(
[id] => 5867670
[patent_doc_number] => 20060162287
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-27
[patent_title] => 'Anisotropic conductive sheet'
[patent_app_type] => utility
[patent_app_number] => 10/547001
[patent_app_country] => US
[patent_app_date] => 2004-02-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0162/20060162287.pdf
[firstpage_image] =>[orig_patent_app_number] => 10547001
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/547001 | Anisotropic conductive sheet | Feb 26, 2004 | Abandoned |
Array
(
[id] => 7176637
[patent_doc_number] => 20050189608
[patent_country] => US
[patent_kind] => A1
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[patent_title] => '[SHALLOW TRENCH ISOLATION AND METHOD OF FORMING THE SAME]'
[patent_app_type] => utility
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[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0189/20050189608.pdf
[firstpage_image] =>[orig_patent_app_number] => 10708372
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/708372 | [SHALLOW TRENCH ISOLATION AND METHOD OF FORMING THE SAME] | Feb 25, 2004 | Abandoned |