
Matthew Grubb
Examiner (ID: 12808)
| Most Active Art Unit | 2838 |
| Art Unit(s) | 2838, 4126 |
| Total Applications | 245 |
| Issued Applications | 194 |
| Pending Applications | 0 |
| Abandoned Applications | 54 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3700179
[patent_doc_number] => 05644698
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-01
[patent_title] => 'Configurable reuse delay criterion for storage volumes'
[patent_app_type] => 1
[patent_app_number] => 8/655526
[patent_app_country] => US
[patent_app_date] => 1996-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 5993
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 230
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/644/05644698.pdf
[firstpage_image] =>[orig_patent_app_number] => 655526
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/655526 | Configurable reuse delay criterion for storage volumes | May 29, 1996 | Issued |
Array
(
[id] => 3738094
[patent_doc_number] => 05652836
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-29
[patent_title] => 'CPU reset circuit'
[patent_app_type] => 1
[patent_app_number] => 8/651576
[patent_app_country] => US
[patent_app_date] => 1996-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2927
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/652/05652836.pdf
[firstpage_image] =>[orig_patent_app_number] => 651576
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/651576 | CPU reset circuit | May 21, 1996 | Issued |
Array
(
[id] => 3659219
[patent_doc_number] => 05630046
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-13
[patent_title] => 'Fault-tolerant computer architecture'
[patent_app_type] => 1
[patent_app_number] => 8/588599
[patent_app_country] => US
[patent_app_date] => 1996-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 3543
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/630/05630046.pdf
[firstpage_image] =>[orig_patent_app_number] => 588599
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/588599 | Fault-tolerant computer architecture | Jan 17, 1996 | Issued |
Array
(
[id] => 3638038
[patent_doc_number] => 05608868
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-04
[patent_title] => 'Method for securing the display on a screen of mimic diagrams representing the status of a system'
[patent_app_type] => 1
[patent_app_number] => 8/586386
[patent_app_country] => US
[patent_app_date] => 1996-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1778
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/608/05608868.pdf
[firstpage_image] =>[orig_patent_app_number] => 586386
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/586386 | Method for securing the display on a screen of mimic diagrams representing the status of a system | Jan 15, 1996 | Issued |
Array
(
[id] => 3669434
[patent_doc_number] => 05659681
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-19
[patent_title] => 'Bus monitor circuit for switching system'
[patent_app_type] => 1
[patent_app_number] => 8/566597
[patent_app_country] => US
[patent_app_date] => 1995-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 978
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 278
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/659/05659681.pdf
[firstpage_image] =>[orig_patent_app_number] => 566597
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/566597 | Bus monitor circuit for switching system | Dec 3, 1995 | Issued |
Array
(
[id] => 3672372
[patent_doc_number] => 05649098
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-15
[patent_title] => 'Methods and apparatus for disabling a watchdog function'
[patent_app_type] => 1
[patent_app_number] => 8/557848
[patent_app_country] => US
[patent_app_date] => 1995-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4222
[patent_no_of_claims] => 17
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/649/05649098.pdf
[firstpage_image] =>[orig_patent_app_number] => 557848
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/557848 | Methods and apparatus for disabling a watchdog function | Nov 13, 1995 | Issued |
Array
(
[id] => 3672168
[patent_doc_number] => 05592613
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-07
[patent_title] => 'Microcomputer having a program correction function'
[patent_app_type] => 1
[patent_app_number] => 8/544694
[patent_app_country] => US
[patent_app_date] => 1995-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 22
[patent_no_of_words] => 9188
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/592/05592613.pdf
[firstpage_image] =>[orig_patent_app_number] => 544694
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/544694 | Microcomputer having a program correction function | Oct 17, 1995 | Issued |
Array
(
[id] => 3633151
[patent_doc_number] => 05615330
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-25
[patent_title] => 'Recovery method for a high availability data processing system'
[patent_app_type] => 1
[patent_app_number] => 8/543798
[patent_app_country] => US
[patent_app_date] => 1995-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 1653
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/615/05615330.pdf
[firstpage_image] =>[orig_patent_app_number] => 543798
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/543798 | Recovery method for a high availability data processing system | Oct 15, 1995 | Issued |
Array
(
[id] => 3634267
[patent_doc_number] => 05602855
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-11
[patent_title] => 'Integrated test circuit'
[patent_app_type] => 1
[patent_app_number] => 8/542236
[patent_app_country] => US
[patent_app_date] => 1995-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 14189
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/602/05602855.pdf
[firstpage_image] =>[orig_patent_app_number] => 542236
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/542236 | Integrated test circuit | Oct 11, 1995 | Issued |
Array
(
[id] => 3630444
[patent_doc_number] => 05642368
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-24
[patent_title] => 'Error protection for multimode speech coders'
[patent_app_type] => 1
[patent_app_number] => 8/541738
[patent_app_country] => US
[patent_app_date] => 1995-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2228
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/642/05642368.pdf
[firstpage_image] =>[orig_patent_app_number] => 541738
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/541738 | Error protection for multimode speech coders | Oct 10, 1995 | Issued |
Array
(
[id] => 3647361
[patent_doc_number] => 05611042
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-11
[patent_title] => 'Data error detection and correction for a shared SRAM'
[patent_app_type] => 1
[patent_app_number] => 8/541989
[patent_app_country] => US
[patent_app_date] => 1995-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2650
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 390
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/611/05611042.pdf
[firstpage_image] =>[orig_patent_app_number] => 541989
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/541989 | Data error detection and correction for a shared SRAM | Oct 9, 1995 | Issued |
Array
(
[id] => 3525983
[patent_doc_number] => 05513313
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-30
[patent_title] => 'Method for generating hierarchical fault-tolerant mesh architectures'
[patent_app_type] => 1
[patent_app_number] => 8/521645
[patent_app_country] => US
[patent_app_date] => 1995-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[patent_no_of_words] => 8759
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/513/05513313.pdf
[firstpage_image] =>[orig_patent_app_number] => 521645
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/521645 | Method for generating hierarchical fault-tolerant mesh architectures | Aug 30, 1995 | Issued |
Array
(
[id] => 3633120
[patent_doc_number] => 05615328
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-25
[patent_title] => 'PCMCIA SRAM card function using DRAM technology'
[patent_app_type] => 1
[patent_app_number] => 8/521509
[patent_app_country] => US
[patent_app_date] => 1995-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 4200
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/615/05615328.pdf
[firstpage_image] =>[orig_patent_app_number] => 521509
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/521509 | PCMCIA SRAM card function using DRAM technology | Aug 29, 1995 | Issued |
| 08/517116 | METHOD AND APPARATUS FOR PRINTER DIAGNOSTICS | Aug 20, 1995 | Abandoned |
Array
(
[id] => 3529939
[patent_doc_number] => 05577194
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-19
[patent_title] => 'Method of managing defects in flash disk memories'
[patent_app_type] => 1
[patent_app_number] => 8/511990
[patent_app_country] => US
[patent_app_date] => 1995-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 9216
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/577/05577194.pdf
[firstpage_image] =>[orig_patent_app_number] => 511990
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/511990 | Method of managing defects in flash disk memories | Aug 6, 1995 | Issued |
Array
(
[id] => 3521451
[patent_doc_number] => 05588114
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-24
[patent_title] => 'Method and apparatus for passive loopback testing of software-controllable parallel ports'
[patent_app_type] => 1
[patent_app_number] => 8/499016
[patent_app_country] => US
[patent_app_date] => 1995-07-06
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/588/05588114.pdf
[firstpage_image] =>[orig_patent_app_number] => 499016
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/499016 | Method and apparatus for passive loopback testing of software-controllable parallel ports | Jul 5, 1995 | Issued |
Array
(
[id] => 3635675
[patent_doc_number] => 05594863
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-14
[patent_title] => 'Method and apparatus for network file recovery'
[patent_app_type] => 1
[patent_app_number] => 8/494919
[patent_app_country] => US
[patent_app_date] => 1995-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 9233
[patent_no_of_claims] => 54
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/594/05594863.pdf
[firstpage_image] =>[orig_patent_app_number] => 494919
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/494919 | Method and apparatus for network file recovery | Jun 25, 1995 | Issued |
| 08/490349 | COMPUTING UNIT HAVING A PLURALITY OF REDUNDANT COMPUTERS | Jun 13, 1995 | Abandoned |
Array
(
[id] => 3644643
[patent_doc_number] => 05631911
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-20
[patent_title] => 'Integrated test circuit'
[patent_app_type] => 1
[patent_app_number] => 8/476003
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/631/05631911.pdf
[firstpage_image] =>[orig_patent_app_number] => 476003
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/476003 | Integrated test circuit | Jun 6, 1995 | Issued |
Array
(
[id] => 3565633
[patent_doc_number] => 05574849
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'Synchronized data transmission between elements of a processing system'
[patent_app_type] => 1
[patent_app_number] => 8/482628
[patent_app_country] => US
[patent_app_date] => 1995-06-07
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[pdf_file] => patents/05/574/05574849.pdf
[firstpage_image] =>[orig_patent_app_number] => 482628
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/482628 | Synchronized data transmission between elements of a processing system | Jun 6, 1995 | Issued |