| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3679441
[patent_doc_number] => 05600659
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'Low cost symbol error correction coding and decoding'
[patent_app_type] => 1
[patent_app_number] => 7/856421
[patent_app_country] => US
[patent_app_date] => 1992-03-23
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[pdf_file] => patents/05/600/05600659.pdf
[firstpage_image] =>[orig_patent_app_number] => 856421
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/856421 | Low cost symbol error correction coding and decoding | Mar 22, 1992 | Issued |
Array
(
[id] => 3490595
[patent_doc_number] => 05400343
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-21
[patent_title] => 'Apparatus and method for defective column detection for semiconductor memories'
[patent_app_type] => 1
[patent_app_number] => 7/843525
[patent_app_country] => US
[patent_app_date] => 1992-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/400/05400343.pdf
[firstpage_image] =>[orig_patent_app_number] => 843525
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/843525 | Apparatus and method for defective column detection for semiconductor memories | Feb 27, 1992 | Issued |
| 07/831152 | DATA COMMUNICATION APPARATUS HAVING AN ERROR CORRECTION MODE | Feb 4, 1992 | Abandoned |
| 07/818039 | METHOD FOR SYNCHRONIZING RESERVED AREAS IN A REDUNDANT STORAGE ARRAY | Jan 7, 1992 | Abandoned |
Array
(
[id] => 3050530
[patent_doc_number] => 05377198
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-27
[patent_title] => 'JTAG instruction error detection'
[patent_app_type] => 1
[patent_app_number] => 7/799507
[patent_app_country] => US
[patent_app_date] => 1991-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 27
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[patent_words_short_claim] => 288
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/377/05377198.pdf
[firstpage_image] =>[orig_patent_app_number] => 799507
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/799507 | JTAG instruction error detection | Nov 26, 1991 | Issued |
| 07/799270 | INTERMODULE TEST ACROSS SYSTEM BUS UTILIZING SERIAL TEST BUS | Nov 26, 1991 | Abandoned |
| 07/794767 | ENHANCED BOUNDARY-SCAN INTERCONNECT TEST DIAGNOSIS THROUGH UTILIZATION OF BOARD TOPOLOGY DATA | Nov 18, 1991 | Abandoned |
| 07/791957 | CIRCUITRY FOR PROPAGATING TEST MODE SIGNALS ASSOCIATED WITH A MEMORY ARRAY | Nov 12, 1991 | Abandoned |
Array
(
[id] => 3104463
[patent_doc_number] => 05369641
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-29
[patent_title] => 'Method and apparatus for detecting and correcting errors in data on magnetic tape media'
[patent_app_type] => 1
[patent_app_number] => 7/791793
[patent_app_country] => US
[patent_app_date] => 1991-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 10069
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/369/05369641.pdf
[firstpage_image] =>[orig_patent_app_number] => 791793
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/791793 | Method and apparatus for detecting and correcting errors in data on magnetic tape media | Nov 11, 1991 | Issued |
| 07/781987 | SYSTEM AND METHOD FOR ANALYZING LARGE LOGIC TRACE ARRAY | Oct 23, 1991 | Abandoned |
Array
(
[id] => 3112407
[patent_doc_number] => 05315599
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-24
[patent_title] => 'Microprocessor-based monitoring or protection device comprising an analog data acquisition system'
[patent_app_type] => 1
[patent_app_number] => 7/772858
[patent_app_country] => US
[patent_app_date] => 1991-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/315/05315599.pdf
[firstpage_image] =>[orig_patent_app_number] => 772858
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/772858 | Microprocessor-based monitoring or protection device comprising an analog data acquisition system | Oct 7, 1991 | Issued |
Array
(
[id] => 3067294
[patent_doc_number] => 05357519
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-18
[patent_title] => 'Diagnostic system'
[patent_app_type] => 1
[patent_app_number] => 7/771127
[patent_app_country] => US
[patent_app_date] => 1991-10-03
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/357/05357519.pdf
[firstpage_image] =>[orig_patent_app_number] => 771127
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/771127 | Diagnostic system | Oct 2, 1991 | Issued |
Array
(
[id] => 3527011
[patent_doc_number] => 05487147
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-23
[patent_title] => 'Generation of error messages and error recovery for an LL(1) parser'
[patent_app_type] => 1
[patent_app_number] => 7/755270
[patent_app_country] => US
[patent_app_date] => 1991-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 8305
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/487/05487147.pdf
[firstpage_image] =>[orig_patent_app_number] => 755270
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/755270 | Generation of error messages and error recovery for an LL(1) parser | Sep 4, 1991 | Issued |
Array
(
[id] => 3435625
[patent_doc_number] => 05423026
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-06
[patent_title] => 'Method and apparatus for performing control unit level recovery operations'
[patent_app_type] => 1
[patent_app_number] => 7/755200
[patent_app_country] => US
[patent_app_date] => 1991-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 7546
[patent_no_of_claims] => 20
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[pdf_file] => patents/05/423/05423026.pdf
[firstpage_image] =>[orig_patent_app_number] => 755200
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/755200 | Method and apparatus for performing control unit level recovery operations | Sep 4, 1991 | Issued |
| 07/753290 | CHANNEL-INITIATED RETRY AND UNIT CHECK FOR PERIPHERAL DEVICES | Aug 29, 1991 | Abandoned |
| 07/735563 | APPARATUS AND METHOD FOR ERROR DETECTION AND FAULT ISOLATION | Jul 24, 1991 | Abandoned |
Array
(
[id] => 3705383
[patent_doc_number] => 05596583
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-21
[patent_title] => 'Test circuitry, systems and methods'
[patent_app_type] => 1
[patent_app_number] => 7/734344
[patent_app_country] => US
[patent_app_date] => 1991-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[pdf_file] => patents/05/596/05596583.pdf
[firstpage_image] =>[orig_patent_app_number] => 734344
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/734344 | Test circuitry, systems and methods | Jul 18, 1991 | Issued |
Array
(
[id] => 3062617
[patent_doc_number] => 05307354
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-26
[patent_title] => 'Method and apparatus for remote maintenance and error recovery in distributed data processing networks'
[patent_app_type] => 1
[patent_app_number] => 7/708149
[patent_app_country] => US
[patent_app_date] => 1991-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3905
[patent_no_of_claims] => 9
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[pdf_file] => patents/05/307/05307354.pdf
[firstpage_image] =>[orig_patent_app_number] => 708149
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/708149 | Method and apparatus for remote maintenance and error recovery in distributed data processing networks | May 30, 1991 | Issued |
| 07/707333 | TEST-FACILITATING CIRCUIT FOR INFORMATION PROCESSING DEVICES | May 28, 1991 | Abandoned |
Array
(
[id] => 3516475
[patent_doc_number] => 05515383
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-07
[patent_title] => 'Built-in self-test system and method for self test of an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 7/706403
[patent_app_country] => US
[patent_app_date] => 1991-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[pdf_file] => patents/05/515/05515383.pdf
[firstpage_image] =>[orig_patent_app_number] => 706403
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/706403 | Built-in self-test system and method for self test of an integrated circuit | May 27, 1991 | Issued |