Search

Matthew J. Gitlin

Examiner (ID: 12957, Phone: (571)270-5525 , Office: P/3635 )

Most Active Art Unit
3635
Art Unit(s)
3635
Total Applications
638
Issued Applications
450
Pending Applications
0
Abandoned Applications
190

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20332576 [patent_doc_number] => 12462860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Using split word lines and switches for reducing capacitive loading on a memory system [patent_app_type] => utility [patent_app_number] => 18/647743 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 7156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647743 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647743
Using split word lines and switches for reducing capacitive loading on a memory system Apr 25, 2024 Issued
Array ( [id] => 19978713 [patent_doc_number] => 12346188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Optimizing power in a memory device [patent_app_type] => utility [patent_app_number] => 18/643714 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643714 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643714
Optimizing power in a memory device Apr 22, 2024 Issued
Array ( [id] => 19687707 [patent_doc_number] => 20250006252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => DATA PROGRAMMING METHOD AND RELATED MEMORY CONTROLLER AND DATA STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/621085 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621085 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/621085
DATA PROGRAMMING METHOD AND RELATED MEMORY CONTROLLER AND DATA STORAGE DEVICE Mar 27, 2024 Pending
18/620808 MEMORY DEVICE FABRICATION THROUGH WAFER BONDING Mar 27, 2024 Pending
Array ( [id] => 19305236 [patent_doc_number] => 20240233816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/613301 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 560 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613301 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/613301
Lifetime mixed level non-volatile memory system Mar 21, 2024 Issued
Array ( [id] => 19305237 [patent_doc_number] => 20240233817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/613466 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613466 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/613466
Lifetime mixed level non-volatile memory system Mar 21, 2024 Issued
Array ( [id] => 19858752 [patent_doc_number] => 12261613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Divided quad clock-based inter-die clocking in a three-dimensional stacked memory device [patent_app_type] => utility [patent_app_number] => 18/607999 [patent_app_country] => US [patent_app_date] => 2024-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607999 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607999
Divided quad clock-based inter-die clocking in a three-dimensional stacked memory device Mar 17, 2024 Issued
Array ( [id] => 19452363 [patent_doc_number] => 20240312493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => INTEGRATED CIRCUIT INCLUDING BACKSIDE WIRING AND METHOD OF DESIGNING THE SAME [patent_app_type] => utility [patent_app_number] => 18/606790 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606790 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/606790
INTEGRATED CIRCUIT INCLUDING BACKSIDE WIRING AND METHOD OF DESIGNING THE SAME Mar 14, 2024 Pending
Array ( [id] => 19391517 [patent_doc_number] => 20240281387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => MEMORY WITH IMPROVED COMMAND/ADDRESS BUS UTILIZATION [patent_app_type] => utility [patent_app_number] => 18/601725 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601725 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/601725
MEMORY WITH IMPROVED COMMAND/ADDRESS BUS UTILIZATION Mar 10, 2024 Pending
Array ( [id] => 19252475 [patent_doc_number] => 20240203472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => CIRCUIT DESIGN AND LAYOUT WITH HIGH EMBEDDED MEMORY DENSITY [patent_app_type] => utility [patent_app_number] => 18/589540 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15101 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18589540 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/589540
Circuit design and layout with high embedded memory density Feb 27, 2024 Issued
Array ( [id] => 20196539 [patent_doc_number] => 20250273249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => SEMICONDUCTOR STRUCTURE INCLUDING MEMORY SIGNAL TRANSMISSION LINE IN BACKSIDE REDISTRIBUTION [patent_app_type] => utility [patent_app_number] => 18/588008 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18588008 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/588008
SEMICONDUCTOR STRUCTURE INCLUDING MEMORY SIGNAL TRANSMISSION LINE IN BACKSIDE REDISTRIBUTION Feb 26, 2024 Pending
Array ( [id] => 19886675 [patent_doc_number] => 12272399 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-04-08 [patent_title] => Differential programming of two-terminal resistive switching memory with program soaking and adjacent path disablement [patent_app_type] => utility [patent_app_number] => 18/587443 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 21220 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587443 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587443
Differential programming of two-terminal resistive switching memory with program soaking and adjacent path disablement Feb 25, 2024 Issued
Array ( [id] => 19237072 [patent_doc_number] => 20240194267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => MEMORY DEVICE RELATED TO PERFORMING A PROGRAM OPERATION ON MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/583632 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583632 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/583632
MEMORY DEVICE RELATED TO PERFORMING A PROGRAM OPERATION ON MEMORY CELLS Feb 20, 2024 Pending
Array ( [id] => 19740987 [patent_doc_number] => 12217826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Memory array test structure and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/443997 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 78 [patent_no_of_words] => 15058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443997 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443997
Memory array test structure and method of forming the same Feb 15, 2024 Issued
Array ( [id] => 19406853 [patent_doc_number] => 20240290364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => DEVICE AND METHOD FOR IN-MEMORY COMPUTING [patent_app_type] => utility [patent_app_number] => 18/441110 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441110 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441110
Device and method for in-memory computing Feb 13, 2024 Issued
Array ( [id] => 19384325 [patent_doc_number] => 20240274195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => HIGH DENSITY EMBEDDED FLASH CELL ARRAY STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/439744 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439744 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439744
HIGH DENSITY EMBEDDED FLASH CELL ARRAY STRUCTURE Feb 11, 2024 Pending
Array ( [id] => 19406881 [patent_doc_number] => 20240290392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => DECK-BASED ERASE FUNCTION [patent_app_type] => utility [patent_app_number] => 18/437419 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437419 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437419
Deck-based erase function Feb 8, 2024 Issued
Array ( [id] => 19363942 [patent_doc_number] => 20240265976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => NOR Memory Cell with Floating Gate [patent_app_type] => utility [patent_app_number] => 18/429938 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429938 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429938
NOR Memory Cell with Floating Gate Jan 31, 2024 Pending
Array ( [id] => 20139211 [patent_doc_number] => 20250246255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => CROSSBAR CIRCUITS INCLUDING RRAM DEVICES WITH MINIMIZED WRITE DISTURBANCES [patent_app_type] => utility [patent_app_number] => 18/429313 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429313 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429313
CROSSBAR CIRCUITS INCLUDING RRAM DEVICES WITH MINIMIZED WRITE DISTURBANCES Jan 30, 2024 Pending
Array ( [id] => 20141271 [patent_doc_number] => 20250248315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => DOMAIN WALL MOVEMENT ELEMENT, MAGNETORESISTIVE ELEMENT, AND MAGNETIC ARRAY [patent_app_type] => utility [patent_app_number] => 18/426880 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426880 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426880
Domain wall movement element, magnetoresistive element, and magnetic array Jan 29, 2024 Issued
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