Search

Matthew Kremer

Examiner (ID: 17681, Phone: (571)270-3394 , Office: P/3736 )

Most Active Art Unit
3791
Art Unit(s)
3791, 3736
Total Applications
816
Issued Applications
412
Pending Applications
116
Abandoned Applications
301

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18883115 [patent_doc_number] => 20240006484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => CONTACT ARCHITECTURE FOR 2D STACKED NANORIBBON TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/855639 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/855639
CONTACT ARCHITECTURE FOR 2D STACKED NANORIBBON TRANSISTOR Jun 29, 2022 Pending
Array ( [id] => 18440021 [patent_doc_number] => 20230187316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/854181 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854181 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854181
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE Jun 29, 2022 Pending
Array ( [id] => 17933245 [patent_doc_number] => 20220328371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE HAVING DIELECTRIC LAYER EDGE COVERING CIRCUIT CARRIER [patent_app_type] => utility [patent_app_number] => 17/850972 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850972 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/850972
MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE HAVING DIELECTRIC LAYER EDGE COVERING CIRCUIT CARRIER Jun 26, 2022 Pending
Array ( [id] => 20496641 [patent_doc_number] => 12538532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Method of forming a gap under a source/drain feature of a multi-gate device [patent_app_type] => utility [patent_app_number] => 17/848701 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848701 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/848701
Method of forming a gap under a source/drain feature of a multi-gate device Jun 23, 2022 Issued
Array ( [id] => 18238178 [patent_doc_number] => 20230070489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => DOPED TANTALUM-CONTAINING BARRIER FILMS [patent_app_type] => utility [patent_app_number] => 17/845356 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845356 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/845356
DOPED TANTALUM-CONTAINING BARRIER FILMS Jun 20, 2022 Pending
Array ( [id] => 18396762 [patent_doc_number] => 20230164983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/844209 [patent_app_country] => US [patent_app_date] => 2022-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17844209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/844209
METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR MEMORY Jun 19, 2022 Pending
Array ( [id] => 17933597 [patent_doc_number] => 20220328723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => AlN MONOCRYSTAL PLATE [patent_app_type] => utility [patent_app_number] => 17/807395 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17807395 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/807395
AlN MONOCRYSTAL PLATE Jun 16, 2022 Pending
Array ( [id] => 18267534 [patent_doc_number] => 20230088776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => Eutectic Electrode Structure of Flip-chip LED Chip and Flip-chip LED Chip [patent_app_type] => utility [patent_app_number] => 17/806497 [patent_app_country] => US [patent_app_date] => 2022-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806497 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806497
Eutectic Electrode Structure of Flip-chip LED Chip and Flip-chip LED Chip Jun 11, 2022 Pending
Array ( [id] => 18297606 [patent_doc_number] => 20230107292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 17/836152 [patent_app_country] => US [patent_app_date] => 2022-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17836152 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/836152
Circuit element connection pattern and electronic device having the same Jun 8, 2022 Issued
Array ( [id] => 18410719 [patent_doc_number] => 20230172072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => LAYOUT AND PROCESSING METHOD THEREOF, STORAGE MEDIUM, AND PROGRAM PRODUCT [patent_app_type] => utility [patent_app_number] => 17/827778 [patent_app_country] => US [patent_app_date] => 2022-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827778 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/827778
LAYOUT AND PROCESSING METHOD THEREOF, STORAGE MEDIUM, AND PROGRAM PRODUCT May 28, 2022 Abandoned
Array ( [id] => 20134005 [patent_doc_number] => 12376336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Semiconductor device with improved source/drain contact and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/698696 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 73 [patent_no_of_words] => 8371 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698696 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/698696
Semiconductor device with improved source/drain contact and method for forming the same Mar 17, 2022 Issued
Array ( [id] => 17933310 [patent_doc_number] => 20220328436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/697720 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17697720 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/697720
DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF Mar 16, 2022 Pending
Array ( [id] => 18655221 [patent_doc_number] => 20230301072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => METHOD FOR MANUFACTURING MEMORY DEVICE HAVING WORD LINE WITH DUAL CONDUCTIVE MATERIALS [patent_app_type] => utility [patent_app_number] => 17/696058 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696058 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/696058
Method for manufacturing memory device having word line with dual conductive materials Mar 15, 2022 Issued
Array ( [id] => 20691947 [patent_doc_number] => 12622120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 17/696051 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 22040 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696051 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/696051
Display device Mar 15, 2022 Issued
Array ( [id] => 20119700 [patent_doc_number] => 12369439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Method for manufacturing semiconductor device structure including an overlay mark structure [patent_app_type] => utility [patent_app_number] => 17/683845 [patent_app_country] => US [patent_app_date] => 2022-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 6442 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683845 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/683845
Method for manufacturing semiconductor device structure including an overlay mark structure Feb 28, 2022 Issued
Array ( [id] => 20455984 [patent_doc_number] => 12519046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Wafer level packaging having redistribution layer formed utilizing laser direct structuring [patent_app_type] => utility [patent_app_number] => 17/677505 [patent_app_country] => US [patent_app_date] => 2022-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 0 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17677505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/677505
Wafer level packaging having redistribution layer formed utilizing laser direct structuring Feb 21, 2022 Issued
Array ( [id] => 20245932 [patent_doc_number] => 12426277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Embedded double side heating phase change random access memory (PCRAM) device and method of making same [patent_app_type] => utility [patent_app_number] => 17/581252 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 2110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581252 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/581252
Embedded double side heating phase change random access memory (PCRAM) device and method of making same Jan 20, 2022 Issued
Array ( [id] => 18456316 [patent_doc_number] => 20230197598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => INDUCTORS AND TRANSFORMERS FORMED BY BURIED POWER RAILS [patent_app_type] => utility [patent_app_number] => 17/554004 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17554004 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/554004
INDUCTORS AND TRANSFORMERS FORMED BY BURIED POWER RAILS Dec 16, 2021 Pending
Array ( [id] => 18351144 [patent_doc_number] => 20230139255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => FORMATION OF GATE SPACERS FOR STRAINED PMOS GATE-ALL-AROUND TRANSISTOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/517076 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517076 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517076
Formation of gate spacers for strained PMOS gate-all-around transistor structures Nov 1, 2021 Issued
Array ( [id] => 18712863 [patent_doc_number] => 20230335496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => Process for Fabricating a 3D-NAND Flash Memory [patent_app_type] => utility [patent_app_number] => 18/030158 [patent_app_country] => US [patent_app_date] => 2021-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18030158 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/030158
Process for Fabricating a 3D-NAND Flash Memory Oct 7, 2021 Pending
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