
Matthew L. Reames
Examiner (ID: 9123, Phone: (571)272-2408 , Office: P/2893 )
| Most Active Art Unit | 2893 |
| Art Unit(s) | 2893, 2896, 2891 |
| Total Applications | 1527 |
| Issued Applications | 1103 |
| Pending Applications | 144 |
| Abandoned Applications | 309 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17203690
[patent_doc_number] => 20210343785
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-04
[patent_title] => SUPERCONDUCTING COMPOUND QUANTUM COMPUTING CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 17/283037
[patent_app_country] => US
[patent_app_date] => 2019-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11479
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 331
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17283037
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/283037 | Superconducting complex quantum computing circuit | Oct 30, 2019 | Issued |
Array
(
[id] => 16812553
[patent_doc_number] => 20210135108
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-06
[patent_title] => STRUCTURE AND METHOD TO FABRICATE RESISTIVE MEMORY WITH VERTICAL PRE-DETERMINED FILAMENT
[patent_app_type] => utility
[patent_app_number] => 16/670215
[patent_app_country] => US
[patent_app_date] => 2019-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7842
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670215
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/670215 | Structure and method to fabricate resistive memory with vertical pre-determined filament | Oct 30, 2019 | Issued |
Array
(
[id] => 17544171
[patent_doc_number] => 11309305
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-19
[patent_title] => Optical systems fabricated by printing-based assembly
[patent_app_type] => utility
[patent_app_number] => 16/667215
[patent_app_country] => US
[patent_app_date] => 2019-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 86
[patent_figures_cnt] => 94
[patent_no_of_words] => 30516
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667215
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/667215 | Optical systems fabricated by printing-based assembly | Oct 28, 2019 | Issued |
Array
(
[id] => 17295670
[patent_doc_number] => 20210391509
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-16
[patent_title] => Optoelectronic Semiconductor Component and Method for Producing an Optoelectronic Semiconductor Component
[patent_app_type] => utility
[patent_app_number] => 17/287889
[patent_app_country] => US
[patent_app_date] => 2019-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6484
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17287889
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/287889 | Optoelectronic Semiconductor Component and Method for Producing an Optoelectronic Semiconductor Component | Oct 27, 2019 | Abandoned |
Array
(
[id] => 18625760
[patent_doc_number] => 11758827
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-12
[patent_title] => Monofilament for producing an Nb
[patent_app_type] => utility
[patent_app_number] => 16/664123
[patent_app_country] => US
[patent_app_date] => 2019-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9887
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16664123
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/664123 | Monofilament for producing an Nb | Oct 24, 2019 | Issued |
Array
(
[id] => 17011230
[patent_doc_number] => 20210242391
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-05
[patent_title] => MULTIPLE STEP EDGE FABRICATION
[patent_app_type] => utility
[patent_app_number] => 17/262981
[patent_app_country] => US
[patent_app_date] => 2019-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7245
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17262981
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/262981 | Multiple step edge fabrication | Oct 17, 2019 | Issued |
Array
(
[id] => 16699215
[patent_doc_number] => 10949820
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-16
[patent_title] => System and method for encoding IC chips for payment objects
[patent_app_type] => utility
[patent_app_number] => 16/598921
[patent_app_country] => US
[patent_app_date] => 2019-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 9863
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598921
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/598921 | System and method for encoding IC chips for payment objects | Oct 9, 2019 | Issued |
Array
(
[id] => 17926076
[patent_doc_number] => 11469341
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-11
[patent_title] => Optical detection panel, fabricating method thereof and display apparatus
[patent_app_type] => utility
[patent_app_number] => 16/638523
[patent_app_country] => US
[patent_app_date] => 2019-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 9072
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16638523
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/638523 | Optical detection panel, fabricating method thereof and display apparatus | Oct 7, 2019 | Issued |
Array
(
[id] => 17818776
[patent_doc_number] => 11424401
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-08-23
[patent_title] => Phononic devices and methods of manufacturing thereof
[patent_app_type] => utility
[patent_app_number] => 16/585496
[patent_app_country] => US
[patent_app_date] => 2019-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 20
[patent_no_of_words] => 8154
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585496
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/585496 | Phononic devices and methods of manufacturing thereof | Sep 26, 2019 | Issued |
Array
(
[id] => 16684515
[patent_doc_number] => 10944007
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-09
[patent_title] => Silicon on insulator semiconductor device with mixed doped regions
[patent_app_type] => utility
[patent_app_number] => 16/578301
[patent_app_country] => US
[patent_app_date] => 2019-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 28
[patent_no_of_words] => 6943
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578301
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/578301 | Silicon on insulator semiconductor device with mixed doped regions | Sep 20, 2019 | Issued |
Array
(
[id] => 15688133
[patent_doc_number] => 20200098730
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => STACKED MEMORY ROUTING TECHNIQUES
[patent_app_type] => utility
[patent_app_number] => 16/576197
[patent_app_country] => US
[patent_app_date] => 2019-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17115
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16576197
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/576197 | Stacked memory routing techniques | Sep 18, 2019 | Issued |
Array
(
[id] => 16684392
[patent_doc_number] => 10943883
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-03-09
[patent_title] => Planar wafer level fan-out of multi-chip modules having different size chips
[patent_app_type] => utility
[patent_app_number] => 16/576240
[patent_app_country] => US
[patent_app_date] => 2019-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 6816
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16576240
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/576240 | Planar wafer level fan-out of multi-chip modules having different size chips | Sep 18, 2019 | Issued |
Array
(
[id] => 16959185
[patent_doc_number] => 11063068
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-13
[patent_title] => Display apparatus
[patent_app_type] => utility
[patent_app_number] => 16/575917
[patent_app_country] => US
[patent_app_date] => 2019-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 14996
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16575917
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/575917 | Display apparatus | Sep 18, 2019 | Issued |
Array
(
[id] => 18447100
[patent_doc_number] => 11682676
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-20
[patent_title] => Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 16/575808
[patent_app_country] => US
[patent_app_date] => 2019-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 9903
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16575808
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/575808 | Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same | Sep 18, 2019 | Issued |
Array
(
[id] => 16723791
[patent_doc_number] => 20210090938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => INTERCONNECTS HAVING AIR GAP SPACERS
[patent_app_type] => utility
[patent_app_number] => 16/576236
[patent_app_country] => US
[patent_app_date] => 2019-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4434
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16576236
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/576236 | Interconnects having air gap spacers | Sep 18, 2019 | Issued |
Array
(
[id] => 15688411
[patent_doc_number] => 20200098869
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => SILICON CARBIDE DEVICES AND METHODS FOR FORMING SILICON CARBIDE DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/576042
[patent_app_country] => US
[patent_app_date] => 2019-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7825
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16576042
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/576042 | Silicon carbide devices and methods for forming silicon carbide devices | Sep 18, 2019 | Issued |
Array
(
[id] => 15687985
[patent_doc_number] => 20200098656
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => ELECTRONIC COMPONENT-INCORPORATING SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 16/576030
[patent_app_country] => US
[patent_app_date] => 2019-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9323
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16576030
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/576030 | Electronic component-incorporating substrate | Sep 18, 2019 | Issued |
Array
(
[id] => 16723943
[patent_doc_number] => 20210091090
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => MEMORY ARRAY WITH CONTINUOUS DIFFUSION FOR BIT-CELLS AND SUPPORT CIRCUITRY
[patent_app_type] => utility
[patent_app_number] => 16/575954
[patent_app_country] => US
[patent_app_date] => 2019-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4181
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16575954
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/575954 | MEMORY ARRAY WITH CONTINUOUS DIFFUSION FOR BIT-CELLS AND SUPPORT CIRCUITRY | Sep 18, 2019 | Abandoned |
Array
(
[id] => 17181443
[patent_doc_number] => 11158693
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-26
[patent_title] => Display apparatus and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/575845
[patent_app_country] => US
[patent_app_date] => 2019-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 8030
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16575845
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/575845 | Display apparatus and method of manufacturing the same | Sep 18, 2019 | Issued |
Array
(
[id] => 18546306
[patent_doc_number] => 11719653
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-08-08
[patent_title] => Methods and systems for manufacturing superconductor devices
[patent_app_type] => utility
[patent_app_number] => 16/575282
[patent_app_country] => US
[patent_app_date] => 2019-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 4717
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16575282
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/575282 | Methods and systems for manufacturing superconductor devices | Sep 17, 2019 | Issued |