Search

Matthew L. Reames

Examiner (ID: 9123, Phone: (571)272-2408 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2893, 2896, 2891
Total Applications
1527
Issued Applications
1103
Pending Applications
144
Abandoned Applications
309

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17056119 [patent_doc_number] => 20210265553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => A QUANTUM PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/261329 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17261329 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/261329
Quantum processing system Jul 18, 2019 Issued
Array ( [id] => 16586167 [patent_doc_number] => 20210020569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => METHODS AND APPARATUS FOR FORMING DUAL METAL INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 16/516817 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516817 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/516817
Methods and apparatus for forming dual metal interconnects Jul 18, 2019 Issued
Array ( [id] => 17002603 [patent_doc_number] => 11081426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => 3D IC power grid [patent_app_type] => utility [patent_app_number] => 16/516966 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516966 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/516966
3D IC power grid Jul 18, 2019 Issued
Array ( [id] => 16819898 [patent_doc_number] => 11004736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Integrated circuit having a single damascene wiring network [patent_app_type] => utility [patent_app_number] => 16/516775 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5949 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516775 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/516775
Integrated circuit having a single damascene wiring network Jul 18, 2019 Issued
Array ( [id] => 15840803 [patent_doc_number] => 20200135684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/517007 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517007 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517007
SEMICONDUCTOR PACKAGE Jul 18, 2019 Abandoned
Array ( [id] => 16502719 [patent_doc_number] => 10868120 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-15 [patent_title] => Method for making a varactor with hyper-abrupt junction region including a superlattice [patent_app_type] => utility [patent_app_number] => 16/513943 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5769 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513943 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513943
Method for making a varactor with hyper-abrupt junction region including a superlattice Jul 16, 2019 Issued
Array ( [id] => 16536742 [patent_doc_number] => 10879357 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-29 [patent_title] => Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice [patent_app_type] => utility [patent_app_number] => 16/513906 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5749 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513906 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513906
Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice Jul 16, 2019 Issued
Array ( [id] => 16668629 [patent_doc_number] => 10937888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlattices [patent_app_type] => utility [patent_app_number] => 16/513875 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5810 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513875 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513875
Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlattices Jul 16, 2019 Issued
Array ( [id] => 15442751 [patent_doc_number] => 20200035559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => WAFER PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 16/513988 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513988 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513988
Wafer processing method Jul 16, 2019 Issued
Array ( [id] => 16586348 [patent_doc_number] => 20210020750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => METHOD FOR MAKING SEMICONDUCTOR DEVICES WITH HYPER-ABRUPT JUNCTION REGION INCLUDING SPACED-APART SUPERLATTICES [patent_app_type] => utility [patent_app_number] => 16/513832 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513832 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513832
Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices Jul 16, 2019 Issued
Array ( [id] => 16586419 [patent_doc_number] => 20210020821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => Multifunctional Quantum Node Device and Methods [patent_app_type] => utility [patent_app_number] => 16/513387 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513387 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513387
Multifunctional Quantum Node Device and Methods Jul 15, 2019 Abandoned
Array ( [id] => 16249387 [patent_doc_number] => 10748762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Process for fabricating at least one semiconductor structure comprising a step of separation relative to the growth substrate [patent_app_type] => utility [patent_app_number] => 16/508503 [patent_app_country] => US [patent_app_date] => 2019-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 6170 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16508503 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/508503
Process for fabricating at least one semiconductor structure comprising a step of separation relative to the growth substrate Jul 10, 2019 Issued
Array ( [id] => 15625553 [patent_doc_number] => 20200083181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/507076 [patent_app_country] => US [patent_app_date] => 2019-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16507076 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/507076
Method for manufacturing semiconductor device Jul 9, 2019 Issued
Array ( [id] => 16264608 [patent_doc_number] => 10756053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-25 [patent_title] => Method of transferring micro devices and device transfer assembly [patent_app_type] => utility [patent_app_number] => 16/507056 [patent_app_country] => US [patent_app_date] => 2019-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4373 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16507056 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/507056
Method of transferring micro devices and device transfer assembly Jul 9, 2019 Issued
Array ( [id] => 15030557 [patent_doc_number] => 20190326283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/447973 [patent_app_country] => US [patent_app_date] => 2019-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447973 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447973
Fin-type field effect transistor structure and manufacturing method thereof Jun 20, 2019 Issued
Array ( [id] => 16527844 [patent_doc_number] => 20200401924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => MODULAR, FREQUENCY-FLEXIBLE, SUPERCONDUCTING QUANTUM PROCESSOR ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/449239 [patent_app_country] => US [patent_app_date] => 2019-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16449239 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/449239
Modular, frequency-flexible, superconducting quantum processor architecture Jun 20, 2019 Issued
Array ( [id] => 16527842 [patent_doc_number] => 20200401922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => QUBIT ASSEMBLY HAVING ADJUSTABLE CURRENT OPERATORS [patent_app_type] => utility [patent_app_number] => 16/445889 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4532 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445889 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/445889
Qubit assembly having adjustable current operators Jun 18, 2019 Issued
Array ( [id] => 16527843 [patent_doc_number] => 20200401923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => SYSTEM AND METHOD FOR LATENCY-AWARE MAPPING OF QUANTUM CIRCUITS TO QUANTUM CHIPS [patent_app_type] => utility [patent_app_number] => 16/446426 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16446426 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/446426
System and method for latency-aware mapping of quantum circuits to quantum chips Jun 18, 2019 Issued
Array ( [id] => 17468784 [patent_doc_number] => 11275260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Reprogrammable quantum processor architecture incorporating calibration loops [patent_app_type] => utility [patent_app_number] => 16/446262 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 53 [patent_no_of_words] => 17385 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16446262 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/446262
Reprogrammable quantum processor architecture incorporating calibration loops Jun 18, 2019 Issued
Array ( [id] => 14904839 [patent_doc_number] => 20190296185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => SOLID-STATE TRANSDUCER DEVICES WITH OPTICALLY-TRANSMISSIVE CARRIER SUBSTRATES AND RELATED SYSTEMS, METHODS, AND DEVICES [patent_app_type] => utility [patent_app_number] => 16/441477 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441477 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441477
SOLID-STATE TRANSDUCER DEVICES WITH OPTICALLY-TRANSMISSIVE CARRIER SUBSTRATES AND RELATED SYSTEMS, METHODS, AND DEVICES Jun 13, 2019 Abandoned
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