Matthew L. Reames

Array ( [id] => 16372724 [patent_doc_number] => 10804490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 15/997595 [patent_app_country] => US [patent_app_date] => 2018-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6665 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15997595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14049861 [patent_doc_number] => 20190081038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => DECOUPLING CAPACITOR CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/997351 [patent_app_country] => US [patent_app_date] => 2018-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15997351 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15315817 [patent_doc_number] => 10522626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Silicon-on-insulator backside contacts [patent_app_type] => utility [patent_app_number] => 15/993679 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5377 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16148413 [patent_doc_number] => 10707288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => TFT array substrate and OLED display panel [patent_app_type] => utility [patent_app_number] => 15/993963 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2496 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993963 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15229979 [patent_doc_number] => 10502707 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-10 [patent_title] => Differential sensing with bioFET sensors [patent_app_type] => utility [patent_app_number] => 15/994802 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 26031 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15218513 [patent_doc_number] => 20190371943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => SILICON ON INSULATOR SEMICONDUCTOR DEVICE WITH MIXED DOPED REGIONS [patent_app_type] => utility [patent_app_number] => 15/992766 [patent_app_country] => US [patent_app_date] => 2018-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15992766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13963635 [patent_doc_number] => 20190058162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => PACKAGING STRUCTURE OF OLED DEVICE AND OLED DEVICE [patent_app_type] => utility [patent_app_number] => 15/992880 [patent_app_country] => US [patent_app_date] => 2018-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3847 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15992880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14301041 [patent_doc_number] => 10290652 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-14 [patent_title] => Three-dimensional memory device with graded word lines and methods of making the same [patent_app_type] => utility [patent_app_number] => 15/992603 [patent_app_country] => US [patent_app_date] => 2018-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 46 [patent_no_of_words] => 19894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15992603 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15185073 [patent_doc_number] => 20190363128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => THREE-DIMENSIONAL INTEGRATION FOR QUBITS ON CRYSTALLINE DIELECTRIC [patent_app_type] => utility [patent_app_number] => 15/989925 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989925 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15234731 [patent_doc_number] => 10505096 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-10 [patent_title] => Three-dimensional integration for qubits on multiple height crystalline dielectric [patent_app_type] => utility [patent_app_number] => 15/989873 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13957 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14476305 [patent_doc_number] => 20190189801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => CAPACITIVE TUNING USING BACKSIDE GATE [patent_app_type] => utility [patent_app_number] => 15/988987 [patent_app_country] => US [patent_app_date] => 2018-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15988987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14558329 [patent_doc_number] => 10347635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Apparatuses comprising memory cells, and apparatuses comprising memory arrays [patent_app_type] => utility [patent_app_number] => 15/986628 [patent_app_country] => US [patent_app_date] => 2018-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7775 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15986628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14955251 [patent_doc_number] => 10438904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/984548 [patent_app_country] => US [patent_app_date] => 2018-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 6180 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15984548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13435191 [patent_doc_number] => 20180269138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => PACKAGED SEMICONDUCTOR DEVICES WITH LASER GROOVED WETTABLE FLANK AND METHODS OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 15/982616 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15200431 [patent_doc_number] => 10497718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Silicon-on-insulator structure having bipolar stress, and manufacturing method therefor [patent_app_type] => utility [patent_app_number] => 15/981921 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4289 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15286475 [patent_doc_number] => 10515907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Three-dimensional memory device containing hydrogen diffusion blocking structures and method of making the same [patent_app_type] => utility [patent_app_number] => 15/982188 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 77 [patent_no_of_words] => 36635 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14707205 [patent_doc_number] => 10381362 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-13 [patent_title] => Three-dimensional memory device including inverted memory stack structures and methods of making the same [patent_app_type] => utility [patent_app_number] => 15/979885 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 56 [patent_no_of_words] => 20696 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13785661 [patent_doc_number] => 20190006369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/979476 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14985285 [patent_doc_number] => 10446564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Non-volatile memory allowing a high integration density [patent_app_type] => utility [patent_app_number] => 15/977357 [patent_app_country] => US [patent_app_date] => 2018-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5414 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15977357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14859499 [patent_doc_number] => 10418486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Integrated circuit chip with strained NMOS and PMOS transistors [patent_app_type] => utility [patent_app_number] => 15/976452 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 52 [patent_no_of_words] => 5987 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976452 [rel_patent_id] =>[rel_patent_doc_number] =>)