Search

Matthew L. Reames

Examiner (ID: 9123, Phone: (571)272-2408 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2893, 2896, 2891
Total Applications
1527
Issued Applications
1103
Pending Applications
144
Abandoned Applications
309

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14955531 [patent_doc_number] => 10439045 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-08 [patent_title] => Flipped VFET with self-aligned junctions and controlled gate length [patent_app_type] => utility [patent_app_number] => 15/974728 [patent_app_country] => US [patent_app_date] => 2018-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 6164 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15974728 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/974728
Flipped VFET with self-aligned junctions and controlled gate length May 8, 2018 Issued
Array ( [id] => 13571377 [patent_doc_number] => 20180337236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => TRENCH POWER SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/975023 [patent_app_country] => US [patent_app_date] => 2018-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15975023 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/975023
Trench power semiconductor component and method of manufacturing the same May 8, 2018 Issued
Array ( [id] => 13558811 [patent_doc_number] => 20180330953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/974476 [patent_app_country] => US [patent_app_date] => 2018-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15974476 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/974476
Semiconductor device and fabrication method thereof May 7, 2018 Issued
Array ( [id] => 15123539 [patent_doc_number] => 20190348403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => STRUCTURE AND METHOD TO FORM NANOSHEET DEVICES WITH BOTTOM ISOLATION [patent_app_type] => utility [patent_app_number] => 15/973992 [patent_app_country] => US [patent_app_date] => 2018-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15973992 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/973992
Structure and method to form nanosheet devices with bottom isolation May 7, 2018 Issued
Array ( [id] => 15200405 [patent_doc_number] => 10497705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Bit line gate and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/972216 [patent_app_country] => US [patent_app_date] => 2018-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2076 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15972216 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/972216
Bit line gate and manufacturing method thereof May 5, 2018 Issued
Array ( [id] => 13906375 [patent_doc_number] => 20190042392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => APPARATUS AND METHOD FOR ERROR REDUCTION USING SYMMETRY IN A QUANTUM COMPUTING SYSTEM [patent_app_type] => utility [patent_app_number] => 15/972117 [patent_app_country] => US [patent_app_date] => 2018-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15972117 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/972117
APPARATUS AND METHOD FOR ERROR REDUCTION USING SYMMETRY IN A QUANTUM COMPUTING SYSTEM May 4, 2018 Abandoned
Array ( [id] => 14707185 [patent_doc_number] => 10381352 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-13 [patent_title] => Integrated assemblies which include carbon-doped oxide, and methods of forming integrated assemblies [patent_app_type] => utility [patent_app_number] => 15/971210 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 4916 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15971210 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/971210
Integrated assemblies which include carbon-doped oxide, and methods of forming integrated assemblies May 3, 2018 Issued
Array ( [id] => 13543461 [patent_doc_number] => 20180323277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => FIN-FET DEVICES AND FABRICATION METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 15/971109 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15971109 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/971109
FIN-FET DEVICES AND FABRICATION METHODS THEREOF May 3, 2018 Abandoned
Array ( [id] => 15093277 [patent_doc_number] => 20190341450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => GATE SPACER AND INNER SPACER FORMATION FOR NANOSHEET TRANSISTORS HAVING RELATIVELY SMALL SPACE BETWEEN ADJACENT GATES [patent_app_type] => utility [patent_app_number] => 15/969855 [patent_app_country] => US [patent_app_date] => 2018-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15969855 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/969855
Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between adjacent gates May 2, 2018 Issued
Array ( [id] => 16249542 [patent_doc_number] => 10748917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Semiconductor memory component integrating a nano-battery, semiconductor device including such a component and method using such a device [patent_app_type] => utility [patent_app_number] => 15/970208 [patent_app_country] => US [patent_app_date] => 2018-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 9678 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15970208 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/970208
Semiconductor memory component integrating a nano-battery, semiconductor device including such a component and method using such a device May 2, 2018 Issued
Array ( [id] => 17152690 [patent_doc_number] => 11145781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Light reception/emission element module and sensor device [patent_app_type] => utility [patent_app_number] => 16/605461 [patent_app_country] => US [patent_app_date] => 2018-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7505 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16605461 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/605461
Light reception/emission element module and sensor device Apr 24, 2018 Issued
Array ( [id] => 13515749 [patent_doc_number] => 20180309417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => SEMICONDUCTOR DEVICE AND POWER AMPLIFIER MODULE [patent_app_type] => utility [patent_app_number] => 15/946552 [patent_app_country] => US [patent_app_date] => 2018-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15946552 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/946552
Semiconductor device and power amplifier module Apr 4, 2018 Issued
Array ( [id] => 13907521 [patent_doc_number] => 20190042965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => APPARATUS AND METHOD FOR A FIELD PROGRAMMABLE QUANTUM ARRAY [patent_app_type] => utility [patent_app_number] => 15/942300 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15942300 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/942300
APPARATUS AND METHOD FOR A FIELD PROGRAMMABLE QUANTUM ARRAY Mar 29, 2018 Abandoned
Array ( [id] => 16516147 [patent_doc_number] => 20200395405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => REDUCING PARASITIC CAPACITANCE IN A QUBIT SYSTEM [patent_app_type] => utility [patent_app_number] => 16/977673 [patent_app_country] => US [patent_app_date] => 2018-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16977673 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/977673
Reducing parasitic capacitance in a qubit system Mar 25, 2018 Issued
Array ( [id] => 15985263 [patent_doc_number] => 10672971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Vertical transmon qubit device with microstrip waveguides [patent_app_type] => utility [patent_app_number] => 15/934348 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11122 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15934348 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/934348
Vertical transmon qubit device with microstrip waveguides Mar 22, 2018 Issued
Array ( [id] => 14904891 [patent_doc_number] => 20190296211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => REDUCING QUBIT FREQUENCY COLLISIONS THROUGH LATTICE DESIGN [patent_app_type] => utility [patent_app_number] => 15/934457 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15934457 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/934457
Reducing qubit frequency collisions through lattice design Mar 22, 2018 Issued
Array ( [id] => 13321007 [patent_doc_number] => 20180212041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => DEVICES AND METHODS FOR A POWER TRANSISTOR HAVING A SCHOTTKY OR SCHOTTKY-LIKE CONTACT [patent_app_type] => utility [patent_app_number] => 15/927693 [patent_app_country] => US [patent_app_date] => 2018-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15927693 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/927693
Devices and methods for a power transistor having a Schottky or Schottky-like contact Mar 20, 2018 Issued
Array ( [id] => 20539077 [patent_doc_number] => 12556157 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2026-02-17 [patent_title] => Laterally-doped MEMS resonator with piezoelectric layer [patent_app_type] => utility [patent_app_number] => 15/912551 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 1089 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15912551 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/912551
Laterally-doped MEMS resonator with piezoelectric layer Mar 4, 2018 Issued
Array ( [id] => 16293814 [patent_doc_number] => 10770672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Flexible OLED device, method for manufacturing same, and support substrate [patent_app_type] => utility [patent_app_number] => 16/610975 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 8507 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16610975 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/610975
Flexible OLED device, method for manufacturing same, and support substrate Feb 26, 2018 Issued
Array ( [id] => 15326943 [patent_doc_number] => 20200003801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => Passive Semiconductor Device Assembly Technology [patent_app_type] => utility [patent_app_number] => 16/486690 [patent_app_country] => US [patent_app_date] => 2018-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8716 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16486690 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/486690
Passive semiconductor device assembly technology Feb 14, 2018 Issued
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