Search

Matthew Laverne Whipple

Examiner (ID: 1192)

Most Active Art Unit
2813
Art Unit(s)
1109, 2813, 1763, 1104
Total Applications
304
Issued Applications
237
Pending Applications
21
Abandoned Applications
46

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3742895 [patent_doc_number] => 05801092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Method of making two-component nanospheres and their use as a low dielectric constant material for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/923490 [patent_app_country] => US [patent_app_date] => 1997-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4753 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801092.pdf [firstpage_image] =>[orig_patent_app_number] => 923490 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/923490
Method of making two-component nanospheres and their use as a low dielectric constant material for semiconductor devices Sep 3, 1997 Issued
Array ( [id] => 3996772 [patent_doc_number] => 05911111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Polysilicon polish for patterning improvement' [patent_app_type] => 1 [patent_app_number] => 8/944041 [patent_app_country] => US [patent_app_date] => 1997-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4395 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911111.pdf [firstpage_image] =>[orig_patent_app_number] => 944041 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/944041
Polysilicon polish for patterning improvement Sep 1, 1997 Issued
Array ( [id] => 3759895 [patent_doc_number] => 05843838 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Modified clean recipe to suppress formation of BPSG bubble' [patent_app_type] => 1 [patent_app_number] => 8/921093 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1258 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/843/05843838.pdf [firstpage_image] =>[orig_patent_app_number] => 921093 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/921093
Modified clean recipe to suppress formation of BPSG bubble Aug 28, 1997 Issued
Array ( [id] => 3888697 [patent_doc_number] => 05834322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Heat treatment of Si single crystal' [patent_app_type] => 1 [patent_app_number] => 8/916291 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2229 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834322.pdf [firstpage_image] =>[orig_patent_app_number] => 916291 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/916291
Heat treatment of Si single crystal Aug 21, 1997 Issued
Array ( [id] => 4084272 [patent_doc_number] => 06025209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Deep groove structure for semiconductors' [patent_app_type] => 1 [patent_app_number] => 8/909090 [patent_app_country] => US [patent_app_date] => 1997-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1887 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025209.pdf [firstpage_image] =>[orig_patent_app_number] => 909090 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/909090
Deep groove structure for semiconductors Aug 11, 1997 Issued
Array ( [id] => 4015946 [patent_doc_number] => 05923948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Method for sharpening emitter sites using low temperature oxidation processes' [patent_app_type] => 1 [patent_app_number] => 8/908830 [patent_app_country] => US [patent_app_date] => 1997-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4423 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923948.pdf [firstpage_image] =>[orig_patent_app_number] => 908830 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/908830
Method for sharpening emitter sites using low temperature oxidation processes Aug 7, 1997 Issued
Array ( [id] => 3937073 [patent_doc_number] => 05915190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Methods for filling trenches in a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 8/902656 [patent_app_country] => US [patent_app_date] => 1997-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5491 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915190.pdf [firstpage_image] =>[orig_patent_app_number] => 902656 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/902656
Methods for filling trenches in a semiconductor wafer Jul 29, 1997 Issued
Array ( [id] => 3936822 [patent_doc_number] => 05981303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Method of making field emitters with porous silicon' [patent_app_type] => 1 [patent_app_number] => 8/895523 [patent_app_country] => US [patent_app_date] => 1997-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981303.pdf [firstpage_image] =>[orig_patent_app_number] => 895523 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895523
Method of making field emitters with porous silicon Jul 16, 1997 Issued
Array ( [id] => 4214990 [patent_doc_number] => 06110820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Low scratch density chemical mechanical planarization process' [patent_app_type] => 1 [patent_app_number] => 8/874779 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1894 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110820.pdf [firstpage_image] =>[orig_patent_app_number] => 874779 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874779
Low scratch density chemical mechanical planarization process Jun 12, 1997 Issued
Array ( [id] => 3874320 [patent_doc_number] => 05838035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Barrier layer for ferroelectric capacitor integrated on silicon' [patent_app_type] => 1 [patent_app_number] => 8/896508 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4553 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838035.pdf [firstpage_image] =>[orig_patent_app_number] => 896508 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/896508
Barrier layer for ferroelectric capacitor integrated on silicon Jun 9, 1997 Issued
Array ( [id] => 3976676 [patent_doc_number] => 05937323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Sequencing of the recipe steps for the optimal low-k HDP-CVD processing' [patent_app_type] => 1 [patent_app_number] => 8/868286 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10040 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937323.pdf [firstpage_image] =>[orig_patent_app_number] => 868286 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/868286
Sequencing of the recipe steps for the optimal low-k HDP-CVD processing Jun 2, 1997 Issued
Array ( [id] => 3991336 [patent_doc_number] => 05891800 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Method for depositing a flow fill layer on an integrated circuit wafer' [patent_app_type] => 1 [patent_app_number] => 8/864365 [patent_app_country] => US [patent_app_date] => 1997-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1886 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/891/05891800.pdf [firstpage_image] =>[orig_patent_app_number] => 864365 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/864365
Method for depositing a flow fill layer on an integrated circuit wafer May 27, 1997 Issued
Array ( [id] => 4085361 [patent_doc_number] => 06025280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Use of SiD.sub.4 for deposition of ultra thin and controllable oxides' [patent_app_type] => 1 [patent_app_number] => 8/848109 [patent_app_country] => US [patent_app_date] => 1997-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 6316 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025280.pdf [firstpage_image] =>[orig_patent_app_number] => 848109 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/848109
Use of SiD.sub.4 for deposition of ultra thin and controllable oxides Apr 27, 1997 Issued
Array ( [id] => 3797415 [patent_doc_number] => 05827786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Charged particle deposition of electrically insulating films' [patent_app_type] => 1 [patent_app_number] => 8/853229 [patent_app_country] => US [patent_app_date] => 1997-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3389 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/827/05827786.pdf [firstpage_image] =>[orig_patent_app_number] => 853229 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/853229
Charged particle deposition of electrically insulating films Apr 27, 1997 Issued
Array ( [id] => 4023970 [patent_doc_number] => 05882978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Methods of forming a silicon nitride film, a capacitor dielectric layer and a capacitor' [patent_app_type] => 1 [patent_app_number] => 8/844771 [patent_app_country] => US [patent_app_date] => 1997-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2379 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/882/05882978.pdf [firstpage_image] =>[orig_patent_app_number] => 844771 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/844771
Methods of forming a silicon nitride film, a capacitor dielectric layer and a capacitor Apr 21, 1997 Issued
Array ( [id] => 3938582 [patent_doc_number] => 05872065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Method for depositing low K SI-O-F films using SIF.sub.4 /oxygen chemistry' [patent_app_type] => 1 [patent_app_number] => 8/825880 [patent_app_country] => US [patent_app_date] => 1997-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5648 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872065.pdf [firstpage_image] =>[orig_patent_app_number] => 825880 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/825880
Method for depositing low K SI-O-F films using SIF.sub.4 /oxygen chemistry Apr 1, 1997 Issued
Array ( [id] => 4063066 [patent_doc_number] => 05866476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Methods for forming moisture blocking layers' [patent_app_type] => 1 [patent_app_number] => 8/826483 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2487 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/866/05866476.pdf [firstpage_image] =>[orig_patent_app_number] => 826483 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/826483
Methods for forming moisture blocking layers Mar 26, 1997 Issued
Array ( [id] => 4191784 [patent_doc_number] => 06130164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Semiconductor device having gate oxide formed by selective oxide removal and method of manufacture thereof' [patent_app_type] => 1 [patent_app_number] => 8/825029 [patent_app_country] => US [patent_app_date] => 1997-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3544 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130164.pdf [firstpage_image] =>[orig_patent_app_number] => 825029 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/825029
Semiconductor device having gate oxide formed by selective oxide removal and method of manufacture thereof Mar 25, 1997 Issued
Array ( [id] => 3786167 [patent_doc_number] => 05736454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Method for making a silicon dioxide layer on a silicon substrate by pure water anodization followed by rapid thermal densification' [patent_app_type] => 1 [patent_app_number] => 8/822593 [patent_app_country] => US [patent_app_date] => 1997-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2975 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/736/05736454.pdf [firstpage_image] =>[orig_patent_app_number] => 822593 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/822593
Method for making a silicon dioxide layer on a silicon substrate by pure water anodization followed by rapid thermal densification Mar 19, 1997 Issued
Array ( [id] => 4000255 [patent_doc_number] => 05858809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Conductive plane beneath suspended microstructure' [patent_app_type] => 1 [patent_app_number] => 8/820316 [patent_app_country] => US [patent_app_date] => 1997-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1632 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/858/05858809.pdf [firstpage_image] =>[orig_patent_app_number] => 820316 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/820316
Conductive plane beneath suspended microstructure Mar 17, 1997 Issued
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