Search

Matthew Laverne Whipple

Examiner (ID: 1192)

Most Active Art Unit
2813
Art Unit(s)
1109, 2813, 1763, 1104
Total Applications
304
Issued Applications
237
Pending Applications
21
Abandoned Applications
46

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4191123 [patent_doc_number] => 06130118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Plasma reaction apparatus and plasma reaction' [patent_app_type] => 1 [patent_app_number] => 8/804294 [patent_app_country] => US [patent_app_date] => 1997-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130118.pdf [firstpage_image] =>[orig_patent_app_number] => 804294 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/804294
Plasma reaction apparatus and plasma reaction Mar 2, 1997 Issued
Array ( [id] => 4042550 [patent_doc_number] => 05874356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Method for forming zig-zag bordered openings in semiconductor structures' [patent_app_type] => 1 [patent_app_number] => 8/795952 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2910 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874356.pdf [firstpage_image] =>[orig_patent_app_number] => 795952 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/795952
Method for forming zig-zag bordered openings in semiconductor structures Feb 27, 1997 Issued
Array ( [id] => 3870276 [patent_doc_number] => 05763329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method for making semiconductor device by coating an SOG film in amine gas atmosphere' [patent_app_type] => 1 [patent_app_number] => 8/806666 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2089 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/763/05763329.pdf [firstpage_image] =>[orig_patent_app_number] => 806666 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/806666
Method for making semiconductor device by coating an SOG film in amine gas atmosphere Feb 25, 1997 Issued
Array ( [id] => 3942121 [patent_doc_number] => 05990000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method and apparatus for improving gap-fill capability using chemical and physical etchbacks' [patent_app_type] => 1 [patent_app_number] => 8/803304 [patent_app_country] => US [patent_app_date] => 1997-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 8444 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/990/05990000.pdf [firstpage_image] =>[orig_patent_app_number] => 803304 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/803304
Method and apparatus for improving gap-fill capability using chemical and physical etchbacks Feb 19, 1997 Issued
Array ( [id] => 4016762 [patent_doc_number] => 05924005 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Process for forming a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/801328 [patent_app_country] => US [patent_app_date] => 1997-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2697 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/924/05924005.pdf [firstpage_image] =>[orig_patent_app_number] => 801328 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/801328
Process for forming a semiconductor device Feb 17, 1997 Issued
Array ( [id] => 3996743 [patent_doc_number] => 05911109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Method of forming an integrated circuit including filling and planarizing a trench having an oxygen barrier layer' [patent_app_type] => 1 [patent_app_number] => 8/800012 [patent_app_country] => US [patent_app_date] => 1997-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 4028 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911109.pdf [firstpage_image] =>[orig_patent_app_number] => 800012 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/800012
Method of forming an integrated circuit including filling and planarizing a trench having an oxygen barrier layer Feb 12, 1997 Issued
Array ( [id] => 3858979 [patent_doc_number] => 05792707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Global planarization method for inter level dielectric layers of integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/789721 [patent_app_country] => US [patent_app_date] => 1997-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2982 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792707.pdf [firstpage_image] =>[orig_patent_app_number] => 789721 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789721
Global planarization method for inter level dielectric layers of integrated circuits Jan 26, 1997 Issued
Array ( [id] => 4000241 [patent_doc_number] => 05858808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Process and auxiliary device for fabricating semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/784002 [patent_app_country] => US [patent_app_date] => 1997-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2372 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/858/05858808.pdf [firstpage_image] =>[orig_patent_app_number] => 784002 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/784002
Process and auxiliary device for fabricating semiconductor devices Jan 14, 1997 Issued
Array ( [id] => 4130411 [patent_doc_number] => 06033979 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method of fabricating a semiconductor device with amorphous carbon layer' [patent_app_type] => 1 [patent_app_number] => 8/782573 [patent_app_country] => US [patent_app_date] => 1997-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 14657 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033979.pdf [firstpage_image] =>[orig_patent_app_number] => 782573 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/782573
Method of fabricating a semiconductor device with amorphous carbon layer Jan 9, 1997 Issued
08/778074 METHOD FOR DEPOSITING A FLOW FILL LAYER ON AN INTEGRATED CIRCUIT WAFER Jan 6, 1997 Abandoned
Array ( [id] => 4012769 [patent_doc_number] => 05880029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Method of passivating semiconductor devices and the passivated devices' [patent_app_type] => 1 [patent_app_number] => 8/775054 [patent_app_country] => US [patent_app_date] => 1996-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1845 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880029.pdf [firstpage_image] =>[orig_patent_app_number] => 775054 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/775054
Method of passivating semiconductor devices and the passivated devices Dec 26, 1996 Issued
Array ( [id] => 4012417 [patent_doc_number] => 05880003 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Method of giving a substantially flat surface of a semiconductor device through a polishing operation' [patent_app_type] => 1 [patent_app_number] => 8/773995 [patent_app_country] => US [patent_app_date] => 1996-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 32 [patent_no_of_words] => 5508 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880003.pdf [firstpage_image] =>[orig_patent_app_number] => 773995 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/773995
Method of giving a substantially flat surface of a semiconductor device through a polishing operation Dec 25, 1996 Issued
Array ( [id] => 4059068 [patent_doc_number] => 05913140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Method for reduction of plasma charging damage during chemical vapor deposition' [patent_app_type] => 1 [patent_app_number] => 8/780027 [patent_app_country] => US [patent_app_date] => 1996-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6554 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913140.pdf [firstpage_image] =>[orig_patent_app_number] => 780027 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/780027
Method for reduction of plasma charging damage during chemical vapor deposition Dec 22, 1996 Issued
Array ( [id] => 4017924 [patent_doc_number] => 05902122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Method of manufacturing an ILD layer by plasma treatment before applying SOG' [patent_app_type] => 1 [patent_app_number] => 8/772169 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1481 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/902/05902122.pdf [firstpage_image] =>[orig_patent_app_number] => 772169 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/772169
Method of manufacturing an ILD layer by plasma treatment before applying SOG Dec 19, 1996 Issued
Array ( [id] => 3858907 [patent_doc_number] => 05792702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method for forming a film over a spin-on-glass layer by means of plasma-enhanced chemical-vapor deposition' [patent_app_type] => 1 [patent_app_number] => 8/770170 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1648 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792702.pdf [firstpage_image] =>[orig_patent_app_number] => 770170 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770170
Method for forming a film over a spin-on-glass layer by means of plasma-enhanced chemical-vapor deposition Dec 18, 1996 Issued
Array ( [id] => 3687737 [patent_doc_number] => 05691247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Method for depositing a flow fill layer on an integrated circuit wafer' [patent_app_type] => 1 [patent_app_number] => 8/769853 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1331 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691247.pdf [firstpage_image] =>[orig_patent_app_number] => 769853 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/769853
Method for depositing a flow fill layer on an integrated circuit wafer Dec 18, 1996 Issued
Array ( [id] => 3771942 [patent_doc_number] => 05807792 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Uniform distribution of reactants in a device layer' [patent_app_type] => 1 [patent_app_number] => 8/768826 [patent_app_country] => US [patent_app_date] => 1996-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 6049 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/807/05807792.pdf [firstpage_image] =>[orig_patent_app_number] => 768826 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768826
Uniform distribution of reactants in a device layer Dec 17, 1996 Issued
08/771352 PROCESS FOR FORMING AN INSULATING LAYER Dec 15, 1996 Abandoned
Array ( [id] => 3885927 [patent_doc_number] => 05714408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Method of forming silicon nitride with varied hydrogen concentration' [patent_app_type] => 1 [patent_app_number] => 8/766619 [patent_app_country] => US [patent_app_date] => 1996-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 6674 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/714/05714408.pdf [firstpage_image] =>[orig_patent_app_number] => 766619 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/766619
Method of forming silicon nitride with varied hydrogen concentration Dec 12, 1996 Issued
Array ( [id] => 3791610 [patent_doc_number] => 05780342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Method for fabricating dielectric films for non-volatile electrically erasable memories' [patent_app_type] => 1 [patent_app_number] => 8/760474 [patent_app_country] => US [patent_app_date] => 1996-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 2657 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/780/05780342.pdf [firstpage_image] =>[orig_patent_app_number] => 760474 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/760474
Method for fabricating dielectric films for non-volatile electrically erasable memories Dec 4, 1996 Issued
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