Search

Matthew M. Kim

Supervisory Patent Examiner (ID: 86, Phone: (571)272-4182 , Office: P/2171 )

Most Active Art Unit
2312
Art Unit(s)
2186, 2312, 2114, 2773, 2171, 2751
Total Applications
329
Issued Applications
219
Pending Applications
17
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3626325 [patent_doc_number] => 05535361 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Cache block replacement scheme based on directory control bit set/reset and hit/miss basis in a multiheading multiprocessor environment' [patent_app_type] => 1 [patent_app_number] => 8/066709 [patent_app_country] => US [patent_app_date] => 1993-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7005 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535361.pdf [firstpage_image] =>[orig_patent_app_number] => 066709 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/066709
Cache block replacement scheme based on directory control bit set/reset and hit/miss basis in a multiheading multiprocessor environment May 23, 1993 Issued
Array ( [id] => 3569788 [patent_doc_number] => 05544347 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Data storage system controlled remote data mirroring with respectively maintained data indices' [patent_app_type] => 1 [patent_app_number] => 8/052039 [patent_app_country] => US [patent_app_date] => 1993-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4325 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/544/05544347.pdf [firstpage_image] =>[orig_patent_app_number] => 052039 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/052039
Data storage system controlled remote data mirroring with respectively maintained data indices Apr 22, 1993 Issued
08/051039 PAGE OPEN/CLOSE SCHEME BASED ON HIGH ORDER ADDRESS BIT AND LIKELIHOOD OF PAGE ACCESS Apr 20, 1993 Pending
Array ( [id] => 3660909 [patent_doc_number] => 05638530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-10 [patent_title] => 'Direct memory access scheme using memory with an integrated processor having communication with external devices' [patent_app_type] => 1 [patent_app_number] => 8/049909 [patent_app_country] => US [patent_app_date] => 1993-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 9964 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/638/05638530.pdf [firstpage_image] =>[orig_patent_app_number] => 049909 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/049909
Direct memory access scheme using memory with an integrated processor having communication with external devices Apr 19, 1993 Issued
08/048409 HIERARCHICAL DATA STORAGE SYSTEM EMPLOYING CONTEMPORANEOUS TRANSFER OF DESIGNATED DATA PAGES TO LOONG WRITE AND SHORT READ CYCLE MEMORY Apr 13, 1993 Pending
Array ( [id] => 3016550 [patent_doc_number] => 05375219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-20 [patent_title] => 'Common system with a plurality of processors using a common memory and utilizing an interrupt signal' [patent_app_type] => 1 [patent_app_number] => 8/043587 [patent_app_country] => US [patent_app_date] => 1993-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3232 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/375/05375219.pdf [firstpage_image] =>[orig_patent_app_number] => 043587 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/043587
Common system with a plurality of processors using a common memory and utilizing an interrupt signal Apr 4, 1993 Issued
08/038562 METHOD AND APPARATUS FOR MANAGING VIDEO DATA FOR FASTER DATA ACCESS BY SELECTIVELY CACHING VIDEO DATA Mar 25, 1993 Pending
Array ( [id] => 3595698 [patent_doc_number] => 05581727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control' [patent_app_type] => 1 [patent_app_number] => 8/044379 [patent_app_country] => US [patent_app_date] => 1993-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6235 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581727.pdf [firstpage_image] =>[orig_patent_app_number] => 044379 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/044379
Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control Mar 21, 1993 Issued
Array ( [id] => 3095080 [patent_doc_number] => 05280604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Multiprocessor system sharing expandable virtual memory and common operating system' [patent_app_type] => 1 [patent_app_number] => 8/025813 [patent_app_country] => US [patent_app_date] => 1993-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3868 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/280/05280604.pdf [firstpage_image] =>[orig_patent_app_number] => 025813 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/025813
Multiprocessor system sharing expandable virtual memory and common operating system Mar 2, 1993 Issued
08/027613 DISC SELECTING AND CONTROLLING METHOD Mar 1, 1993 Abandoned
Array ( [id] => 3636545 [patent_doc_number] => 05603003 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'High speed file access control method and computer system including a plurality of storage subsystems connected on a bus' [patent_app_type] => 1 [patent_app_number] => 8/024462 [patent_app_country] => US [patent_app_date] => 1993-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 59 [patent_no_of_words] => 19908 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/603/05603003.pdf [firstpage_image] =>[orig_patent_app_number] => 024462 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/024462
High speed file access control method and computer system including a plurality of storage subsystems connected on a bus Feb 28, 1993 Issued
Array ( [id] => 3047176 [patent_doc_number] => 05329633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'Cache memory system, and comparator and MOS analog XOR amplifier for use in the system' [patent_app_type] => 1 [patent_app_number] => 8/023965 [patent_app_country] => US [patent_app_date] => 1993-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/329/05329633.pdf [firstpage_image] =>[orig_patent_app_number] => 023965 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/023965
Cache memory system, and comparator and MOS analog XOR amplifier for use in the system Feb 25, 1993 Issued
Array ( [id] => 3047157 [patent_doc_number] => 05329632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'Cache memory system, and comparator and MOS analog XOR amplifier for use in the system' [patent_app_type] => 1 [patent_app_number] => 8/023959 [patent_app_country] => US [patent_app_date] => 1993-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4138 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/329/05329632.pdf [firstpage_image] =>[orig_patent_app_number] => 023959 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/023959
Cache memory system, and comparator and MOS analog XOR amplifier for use in the system Feb 25, 1993 Issued
Array ( [id] => 3050010 [patent_doc_number] => 05301299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Optimized write protocol for memory accesses utilizing row and column strobes' [patent_app_type] => 1 [patent_app_number] => 8/020184 [patent_app_country] => US [patent_app_date] => 1993-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5125 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/301/05301299.pdf [firstpage_image] =>[orig_patent_app_number] => 020184 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/020184
Optimized write protocol for memory accesses utilizing row and column strobes Feb 15, 1993 Issued
08/017976 MEMORY ACCESSING SYSTEM WITH AN INTERFACE AND MEMORY SELECTION UNIT UTILIZING WRITE PROTECT AND STROBE SIGNALS Feb 11, 1993 Abandoned
08/009432 DATA TRANSFER CONTROL CIRCUIT FOR A PARALLEL PROCESSING DEVICE AND METHOD OF OPERATING SAME Jan 26, 1993 Abandoned
08/007159 METHOD AND APPARATUS FOR TRANSFERRING DATA AMONG AN ARBITRARILY LARGE NUMBER OF COMPUTER DEVICES IN A NETWORKED COMPUTER ENVIRONMENT Jan 20, 1993 Abandoned
08/002292 METHOD AND SYSTEM FOR INCREASED SYSTEM MEMORY CONCURRENCY IN A MULTI-PROCESSOR COMPUTER SYSTEM UTILIZING CONCURRENT ACCESS OF REFRENCE AND CHANGE BITS Jan 7, 1993 Abandoned
Array ( [id] => 2963389 [patent_doc_number] => 05263142 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-16 [patent_title] => 'Input/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devices' [patent_app_type] => 1 [patent_app_number] => 7/999193 [patent_app_country] => US [patent_app_date] => 1992-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 16548 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 589 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/263/05263142.pdf [firstpage_image] =>[orig_patent_app_number] => 999193 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/999193
Input/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devices Dec 27, 1992 Issued
Array ( [id] => 3625732 [patent_doc_number] => 05566324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Computer apparatus including a main memory prefetch cache and method of operation thereof' [patent_app_type] => 1 [patent_app_number] => 7/996533 [patent_app_country] => US [patent_app_date] => 1992-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9896 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/566/05566324.pdf [firstpage_image] =>[orig_patent_app_number] => 996533 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/996533
Computer apparatus including a main memory prefetch cache and method of operation thereof Dec 23, 1992 Issued
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