Search

Matthew M. Kim

Supervisory Patent Examiner (ID: 10492, Phone: (571)272-4182 , Office: P/2171 )

Most Active Art Unit
2312
Art Unit(s)
2171, 2186, 2773, 2312, 2114, 2751
Total Applications
329
Issued Applications
219
Pending Applications
17
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3661557 [patent_doc_number] => 05606682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Data processor with branch target address cache and subroutine return address cache and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/418049 [patent_app_country] => US [patent_app_date] => 1995-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 33 [patent_no_of_words] => 7589 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606682.pdf [firstpage_image] =>[orig_patent_app_number] => 418049 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/418049
Data processor with branch target address cache and subroutine return address cache and method of operation Apr 6, 1995 Issued
Array ( [id] => 3839388 [patent_doc_number] => 05732242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Consistently specifying way destinations through prefetching hints' [patent_app_type] => 1 [patent_app_number] => 8/410524 [patent_app_country] => US [patent_app_date] => 1995-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8858 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732242.pdf [firstpage_image] =>[orig_patent_app_number] => 410524 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/410524
Consistently specifying way destinations through prefetching hints Mar 23, 1995 Issued
Array ( [id] => 3625849 [patent_doc_number] => 05535328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Non-volatile memory system card with flash erasable sectors of EEprom cells including a mechanism for substituting defective cells' [patent_app_type] => 1 [patent_app_number] => 8/393569 [patent_app_country] => US [patent_app_date] => 1995-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 9507 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535328.pdf [firstpage_image] =>[orig_patent_app_number] => 393569 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/393569
Non-volatile memory system card with flash erasable sectors of EEprom cells including a mechanism for substituting defective cells Feb 22, 1995 Issued
Array ( [id] => 3503281 [patent_doc_number] => 05561781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'Port swapping for improved virtual SRAM performance and processing of concurrent processor access requests' [patent_app_type] => 1 [patent_app_number] => 8/376275 [patent_app_country] => US [patent_app_date] => 1995-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4422 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561781.pdf [firstpage_image] =>[orig_patent_app_number] => 376275 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/376275
Port swapping for improved virtual SRAM performance and processing of concurrent processor access requests Jan 22, 1995 Issued
Array ( [id] => 3701557 [patent_doc_number] => 05644789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'System and method for handling I/O requests over an interface bus to a storage disk array' [patent_app_type] => 1 [patent_app_number] => 8/376944 [patent_app_country] => US [patent_app_date] => 1995-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3395 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644789.pdf [firstpage_image] =>[orig_patent_app_number] => 376944 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/376944
System and method for handling I/O requests over an interface bus to a storage disk array Jan 18, 1995 Issued
08/372526 METHOD AND APPARATUS FOR PERFORMING ATOMIC TRANSACTIONS IN A SHARED MEMORY MULTIPROCESSOR SYSTEM Jan 12, 1995 Abandoned
Array ( [id] => 3695148 [patent_doc_number] => 05634077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Information processing system with control methods and apparatus for information storage and interrupt request handling scheme' [patent_app_type] => 1 [patent_app_number] => 8/370236 [patent_app_country] => US [patent_app_date] => 1995-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1580 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/634/05634077.pdf [firstpage_image] =>[orig_patent_app_number] => 370236 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/370236
Information processing system with control methods and apparatus for information storage and interrupt request handling scheme Jan 8, 1995 Issued
Array ( [id] => 3647767 [patent_doc_number] => 05611068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Apparatus and method for controlling pipelined data transfer scheme between stages employing shift register and associated addressing mechanism' [patent_app_type] => 1 [patent_app_number] => 8/364889 [patent_app_country] => US [patent_app_date] => 1994-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3036 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/611/05611068.pdf [firstpage_image] =>[orig_patent_app_number] => 364889 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/364889
Apparatus and method for controlling pipelined data transfer scheme between stages employing shift register and associated addressing mechanism Dec 26, 1994 Issued
Array ( [id] => 3744108 [patent_doc_number] => 05636357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Memory card and method for operation in a plurality of systems having incompatible object code format requirements' [patent_app_type] => 1 [patent_app_number] => 8/361056 [patent_app_country] => US [patent_app_date] => 1994-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3285 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/636/05636357.pdf [firstpage_image] =>[orig_patent_app_number] => 361056 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/361056
Memory card and method for operation in a plurality of systems having incompatible object code format requirements Dec 20, 1994 Issued
Array ( [id] => 3495060 [patent_doc_number] => 05446856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Circuitry and method for addressing global array elements in a distributed memory, multiple processor computer' [patent_app_type] => 1 [patent_app_number] => 8/357083 [patent_app_country] => US [patent_app_date] => 1994-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3511 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446856.pdf [firstpage_image] =>[orig_patent_app_number] => 357083 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/357083
Circuitry and method for addressing global array elements in a distributed memory, multiple processor computer Dec 14, 1994 Issued
Array ( [id] => 3507434 [patent_doc_number] => 05509136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'Data processing system including different throughput access sources accessing main storage in same direction' [patent_app_type] => 1 [patent_app_number] => 8/357147 [patent_app_country] => US [patent_app_date] => 1994-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5891 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/509/05509136.pdf [firstpage_image] =>[orig_patent_app_number] => 357147 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/357147
Data processing system including different throughput access sources accessing main storage in same direction Dec 14, 1994 Issued
Array ( [id] => 3673283 [patent_doc_number] => 05649156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Cache management system utilizing a cache data replacer responsive to cache stress threshold value and the period of time a data element remains in cache' [patent_app_type] => 1 [patent_app_number] => 8/353923 [patent_app_country] => US [patent_app_date] => 1994-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 11889 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649156.pdf [firstpage_image] =>[orig_patent_app_number] => 353923 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/353923
Cache management system utilizing a cache data replacer responsive to cache stress threshold value and the period of time a data element remains in cache Dec 11, 1994 Issued
Array ( [id] => 3734331 [patent_doc_number] => 05682500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'System and method for determining sequential cache data access in progress' [patent_app_type] => 1 [patent_app_number] => 8/354241 [patent_app_country] => US [patent_app_date] => 1994-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7724 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682500.pdf [firstpage_image] =>[orig_patent_app_number] => 354241 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/354241
System and method for determining sequential cache data access in progress Dec 11, 1994 Issued
Array ( [id] => 3505593 [patent_doc_number] => 05537568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'System for dynamically controlling cache manager maintaining cache index and controlling sequential data access' [patent_app_type] => 1 [patent_app_number] => 8/354489 [patent_app_country] => US [patent_app_date] => 1994-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5954 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537568.pdf [firstpage_image] =>[orig_patent_app_number] => 354489 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/354489
System for dynamically controlling cache manager maintaining cache index and controlling sequential data access Dec 11, 1994 Issued
08/351759 EXTERNAL MEANS OF CONTROLLING CACHEABILITY ATTRIBUTE OF CPU ACCESSES Dec 7, 1994 Abandoned
08/349226 SHARED L2 SUPPORT FOR INCLUSION PROPERTY IN SPLIT L1 DATA AND INSTRUCTION CACHES Dec 4, 1994 Abandoned
Array ( [id] => 3672452 [patent_doc_number] => 05649102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Distributed shared data management system for controlling structured shared data and for serializing access to shared data' [patent_app_type] => 1 [patent_app_number] => 8/348099 [patent_app_country] => US [patent_app_date] => 1994-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 50 [patent_no_of_words] => 18652 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649102.pdf [firstpage_image] =>[orig_patent_app_number] => 348099 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/348099
Distributed shared data management system for controlling structured shared data and for serializing access to shared data Nov 24, 1994 Issued
Array ( [id] => 3540236 [patent_doc_number] => 05542067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Virtual multi-port RAM employing multiple accesses during single machine cycle' [patent_app_type] => 1 [patent_app_number] => 8/345328 [patent_app_country] => US [patent_app_date] => 1994-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7942 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/542/05542067.pdf [firstpage_image] =>[orig_patent_app_number] => 345328 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/345328
Virtual multi-port RAM employing multiple accesses during single machine cycle Nov 20, 1994 Issued
Array ( [id] => 3527205 [patent_doc_number] => 05487162 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-23 [patent_title] => 'Cache lock information feeding system using an address translator' [patent_app_type] => 1 [patent_app_number] => 8/338818 [patent_app_country] => US [patent_app_date] => 1994-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6596 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/487/05487162.pdf [firstpage_image] =>[orig_patent_app_number] => 338818 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/338818
Cache lock information feeding system using an address translator Nov 9, 1994 Issued
Array ( [id] => 3524107 [patent_doc_number] => 05564040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Method and apparatus for providing a server function in a logically partitioned hardware machine' [patent_app_type] => 1 [patent_app_number] => 8/335609 [patent_app_country] => US [patent_app_date] => 1994-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5110 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/564/05564040.pdf [firstpage_image] =>[orig_patent_app_number] => 335609 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/335609
Method and apparatus for providing a server function in a logically partitioned hardware machine Nov 7, 1994 Issued
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