Search

Matthew M. Kim

Supervisory Patent Examiner (ID: 7108, Phone: (571)272-4182 , Office: P/2171 )

Most Active Art Unit
2312
Art Unit(s)
2171, 2751, 2773, 2186, 2114, 2312
Total Applications
329
Issued Applications
219
Pending Applications
17
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3604886 [patent_doc_number] => 05568651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Method for detection of configuration types and addressing modes of a dynamic RAM' [patent_app_type] => 1 [patent_app_number] => 8/333809 [patent_app_country] => US [patent_app_date] => 1994-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4375 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568651.pdf [firstpage_image] =>[orig_patent_app_number] => 333809 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/333809
Method for detection of configuration types and addressing modes of a dynamic RAM Nov 2, 1994 Issued
Array ( [id] => 3636029 [patent_doc_number] => 05594887 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Main memory controller responsive to signals indicative of owned and unowned status' [patent_app_type] => 1 [patent_app_number] => 8/332759 [patent_app_country] => US [patent_app_date] => 1994-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2070 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594887.pdf [firstpage_image] =>[orig_patent_app_number] => 332759 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/332759
Main memory controller responsive to signals indicative of owned and unowned status Oct 31, 1994 Issued
08/330679 A HIGH PERFORMANCE COMPUTER SYSTEM OF A PARALLEL WRITE BUFFERING TYPE Oct 27, 1994 Abandoned
Array ( [id] => 3661615 [patent_doc_number] => 05606686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Access control method for a shared main memory in a multiprocessor based upon a directory held at a storage location of data in the memory after reading data to a processor' [patent_app_type] => 1 [patent_app_number] => 8/328759 [patent_app_country] => US [patent_app_date] => 1994-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 12280 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606686.pdf [firstpage_image] =>[orig_patent_app_number] => 328759 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/328759
Access control method for a shared main memory in a multiprocessor based upon a directory held at a storage location of data in the memory after reading data to a processor Oct 23, 1994 Issued
Array ( [id] => 3595763 [patent_doc_number] => 05581731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Method and apparatus for managing video data for faster access by selectively caching video data' [patent_app_type] => 1 [patent_app_number] => 8/323420 [patent_app_country] => US [patent_app_date] => 1994-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2268 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581731.pdf [firstpage_image] =>[orig_patent_app_number] => 323420 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/323420
Method and apparatus for managing video data for faster access by selectively caching video data Oct 13, 1994 Issued
Array ( [id] => 3744220 [patent_doc_number] => 05636365 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Hierarchical buffer memories for selectively controlling data coherence including coherence control request means' [patent_app_type] => 1 [patent_app_number] => 8/318439 [patent_app_country] => US [patent_app_date] => 1994-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7107 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/636/05636365.pdf [firstpage_image] =>[orig_patent_app_number] => 318439 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/318439
Hierarchical buffer memories for selectively controlling data coherence including coherence control request means Oct 4, 1994 Issued
Array ( [id] => 3575910 [patent_doc_number] => 05526510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'Method and apparatus for implementing a single clock cycle line replacement in a data cache unit' [patent_app_type] => 1 [patent_app_number] => 8/315889 [patent_app_country] => US [patent_app_date] => 1994-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 12014 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/526/05526510.pdf [firstpage_image] =>[orig_patent_app_number] => 315889 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/315889
Method and apparatus for implementing a single clock cycle line replacement in a data cache unit Sep 29, 1994 Issued
Array ( [id] => 3636594 [patent_doc_number] => 05603006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Cache control unit using a plurality of request stacks' [patent_app_type] => 1 [patent_app_number] => 8/313389 [patent_app_country] => US [patent_app_date] => 1994-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3669 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/603/05603006.pdf [firstpage_image] =>[orig_patent_app_number] => 313389 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/313389
Cache control unit using a plurality of request stacks Sep 26, 1994 Issued
Array ( [id] => 3502788 [patent_doc_number] => 05440718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Single semiconductor substrate RAM device utilizing data compressing/expanding mechanism in a multi-microprocessor environment' [patent_app_type] => 1 [patent_app_number] => 8/308848 [patent_app_country] => US [patent_app_date] => 1994-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 7858 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440718.pdf [firstpage_image] =>[orig_patent_app_number] => 308848 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/308848
Single semiconductor substrate RAM device utilizing data compressing/expanding mechanism in a multi-microprocessor environment Sep 18, 1994 Issued
Array ( [id] => 3626312 [patent_doc_number] => 05535360 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/298989 [patent_app_country] => US [patent_app_date] => 1994-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2563 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535360.pdf [firstpage_image] =>[orig_patent_app_number] => 298989 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/298989
Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor Aug 30, 1994 Issued
Array ( [id] => 3661641 [patent_doc_number] => 05606688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Method and apparatus for dynamic cache memory allocation via single-reference residency times' [patent_app_type] => 1 [patent_app_number] => 8/298826 [patent_app_country] => US [patent_app_date] => 1994-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6448 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606688.pdf [firstpage_image] =>[orig_patent_app_number] => 298826 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/298826
Method and apparatus for dynamic cache memory allocation via single-reference residency times Aug 30, 1994 Issued
Array ( [id] => 3518690 [patent_doc_number] => 05515523 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Method and apparatus for arbitrating conflicts by monitoring number of access requests per unit of time in multiport memory systems' [patent_app_type] => 1 [patent_app_number] => 8/288640 [patent_app_country] => US [patent_app_date] => 1994-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7466 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/515/05515523.pdf [firstpage_image] =>[orig_patent_app_number] => 288640 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/288640
Method and apparatus for arbitrating conflicts by monitoring number of access requests per unit of time in multiport memory systems Aug 9, 1994 Issued
08/285144 METHOD AND DEVICE FOR MANAGING THE RELATIVE DISPLACEMENT OF A CURSOR IN RELATION TO THE IMAGE DISPLAYED ON A VIEWING DEVICE Aug 2, 1994 Abandoned
08/282691 CACHE MEMORY SYSTEM HAVING SECONDARY CACHE INTEGRATED WITH PRIMARY CACHE FOR USE WITH VLSI CIRCUITS Jul 28, 1994 Abandoned
Array ( [id] => 3595836 [patent_doc_number] => 05581736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Method and system for dynamically sharing RAM between virtual memory and disk cache' [patent_app_type] => 1 [patent_app_number] => 8/276269 [patent_app_country] => US [patent_app_date] => 1994-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 9258 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581736.pdf [firstpage_image] =>[orig_patent_app_number] => 276269 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/276269
Method and system for dynamically sharing RAM between virtual memory and disk cache Jul 17, 1994 Issued
Array ( [id] => 3612339 [patent_doc_number] => 05559987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Method and apparatus for updating a duplicate tag status in a snoop bus protocol based computer system' [patent_app_type] => 1 [patent_app_number] => 8/268409 [patent_app_country] => US [patent_app_date] => 1994-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5818 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559987.pdf [firstpage_image] =>[orig_patent_app_number] => 268409 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/268409
Method and apparatus for updating a duplicate tag status in a snoop bus protocol based computer system Jun 29, 1994 Issued
Array ( [id] => 3625746 [patent_doc_number] => 05566325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Method and apparatus for adaptive memory access' [patent_app_type] => 1 [patent_app_number] => 8/269259 [patent_app_country] => US [patent_app_date] => 1994-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4229 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/566/05566325.pdf [firstpage_image] =>[orig_patent_app_number] => 269259 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/269259
Method and apparatus for adaptive memory access Jun 29, 1994 Issued
Array ( [id] => 3622423 [patent_doc_number] => 05590381 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Method and apparatus for buffered video playback of video content distributed on a plurality of disks' [patent_app_type] => 1 [patent_app_number] => 8/268599 [patent_app_country] => US [patent_app_date] => 1994-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4437 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590381.pdf [firstpage_image] =>[orig_patent_app_number] => 268599 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/268599
Method and apparatus for buffered video playback of video content distributed on a plurality of disks Jun 29, 1994 Issued
08/258352 INCREMENTAL COMPUTER FILE BACKUP USING SIGNATURES Jun 8, 1994 Abandoned
Array ( [id] => 3700093 [patent_doc_number] => 05696917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 8/253499 [patent_app_country] => US [patent_app_date] => 1994-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 18436 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696917.pdf [firstpage_image] =>[orig_patent_app_number] => 253499 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/253499
Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory Jun 2, 1994 Issued
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