Search

Matthew M. Kim

Supervisory Patent Examiner (ID: 7736, Phone: (571)272-4182 , Office: P/2171 )

Most Active Art Unit
2312
Art Unit(s)
2773, 2114, 2186, 2312, 2171, 2751
Total Applications
329
Issued Applications
219
Pending Applications
17
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3671296 [patent_doc_number] => 05627995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Data compression and decompression using memory spaces of more than one size' [patent_app_type] => 1 [patent_app_number] => 8/251465 [patent_app_country] => US [patent_app_date] => 1994-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 11770 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627995.pdf [firstpage_image] =>[orig_patent_app_number] => 251465 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/251465
Data compression and decompression using memory spaces of more than one size May 31, 1994 Issued
08/252546 DISC SELECTING AND CONTROLLING METHOD May 31, 1994 Abandoned
08/247139 SET ASSOCIATIVE BLOCK MANAGEMENT DISK CACHE May 19, 1994 Abandoned
Array ( [id] => 3503244 [patent_doc_number] => 05561779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'Processor board having a second level writeback cache system and a third level writethrough cache system which stores exclusive state information for use in a multiprocessor computer system' [patent_app_type] => 1 [patent_app_number] => 8/237779 [patent_app_country] => US [patent_app_date] => 1994-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 10119 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561779.pdf [firstpage_image] =>[orig_patent_app_number] => 237779 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/237779
Processor board having a second level writeback cache system and a third level writethrough cache system which stores exclusive state information for use in a multiprocessor computer system May 3, 1994 Issued
08/235079 OPERATOR-COMMUNICATIONS INTERFACE FOR A MANUAL DATA STORAGE LIBRARY Apr 28, 1994 Abandoned
Array ( [id] => 3585548 [patent_doc_number] => 05539891 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Data transfer control circuit with a sequencer circuit and control subcircuits and data control method for successively entering data into a memory' [patent_app_type] => 1 [patent_app_number] => 8/234508 [patent_app_country] => US [patent_app_date] => 1994-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 77 [patent_no_of_words] => 32198 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539891.pdf [firstpage_image] =>[orig_patent_app_number] => 234508 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/234508
Data transfer control circuit with a sequencer circuit and control subcircuits and data control method for successively entering data into a memory Apr 27, 1994 Issued
08/231479 SYSTEM FOR MANAGEMENT OF LIMITING AMOUNT OF USE OF SOFTWARE AND LIMITING NUMBER OF BACKUP COPIES EMPLOYING MEMORY PROCESSING UNIT REGULATION INFORMATION Apr 21, 1994 Abandoned
Array ( [id] => 3604630 [patent_doc_number] => 05568634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Method of writing in a non-volatile memory, notably in a memory card employing memory allocation strategies on size and occupancy basis' [patent_app_type] => 1 [patent_app_number] => 8/231019 [patent_app_country] => US [patent_app_date] => 1994-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 5104 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568634.pdf [firstpage_image] =>[orig_patent_app_number] => 231019 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/231019
Method of writing in a non-volatile memory, notably in a memory card employing memory allocation strategies on size and occupancy basis Apr 20, 1994 Issued
Array ( [id] => 3564332 [patent_doc_number] => 05572698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'System and method for allocating memory resources where the category of a memory resource determines where on a circular stack a pointer to the memory resource is placed' [patent_app_type] => 1 [patent_app_number] => 8/228989 [patent_app_country] => US [patent_app_date] => 1994-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 5022 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572698.pdf [firstpage_image] =>[orig_patent_app_number] => 228989 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/228989
System and method for allocating memory resources where the category of a memory resource determines where on a circular stack a pointer to the memory resource is placed Apr 17, 1994 Issued
Array ( [id] => 3053393 [patent_doc_number] => 05377345 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Methods and apparatus for providing multiple pending operations in a cache consistent multiple processor computer system' [patent_app_type] => 1 [patent_app_number] => 8/227188 [patent_app_country] => US [patent_app_date] => 1994-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6594 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/377/05377345.pdf [firstpage_image] =>[orig_patent_app_number] => 227188 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/227188
Methods and apparatus for providing multiple pending operations in a cache consistent multiple processor computer system Apr 12, 1994 Issued
Array ( [id] => 3563213 [patent_doc_number] => 05548795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Method for determining command execution dependencies within command queue reordering process' [patent_app_type] => 1 [patent_app_number] => 8/218567 [patent_app_country] => US [patent_app_date] => 1994-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 6089 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548795.pdf [firstpage_image] =>[orig_patent_app_number] => 218567 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/218567
Method for determining command execution dependencies within command queue reordering process Mar 27, 1994 Issued
08/215217 DISK ACCELERATOR Mar 20, 1994 Abandoned
08/208987 METHOD AND APPARATUS FOR PERFORMING PIPELINE STORE INSTRUCTIONS USING A SINGLE CACHE ACCESS PIPESTAGE Mar 8, 1994 Abandoned
Array ( [id] => 4422555 [patent_doc_number] => 06272610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'File memory device using flash memories, and an information processing system using the same' [patent_app_type] => 1 [patent_app_number] => 8/207749 [patent_app_country] => US [patent_app_date] => 1994-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 9648 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272610.pdf [firstpage_image] =>[orig_patent_app_number] => 207749 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/207749
File memory device using flash memories, and an information processing system using the same Mar 8, 1994 Issued
Array ( [id] => 3473435 [patent_doc_number] => 05392417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Processor cycle tracking in a controller for two-way set associative cache' [patent_app_type] => 1 [patent_app_number] => 8/205129 [patent_app_country] => US [patent_app_date] => 1994-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4633 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392417.pdf [firstpage_image] =>[orig_patent_app_number] => 205129 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/205129
Processor cycle tracking in a controller for two-way set associative cache Feb 28, 1994 Issued
Array ( [id] => 3590437 [patent_doc_number] => 05491810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-13 [patent_title] => 'Method and system for automated data storage system space allocation utilizing prioritized data set parameters' [patent_app_type] => 1 [patent_app_number] => 8/204107 [patent_app_country] => US [patent_app_date] => 1994-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5541 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/491/05491810.pdf [firstpage_image] =>[orig_patent_app_number] => 204107 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/204107
Method and system for automated data storage system space allocation utilizing prioritized data set parameters Feb 28, 1994 Issued
Array ( [id] => 3502652 [patent_doc_number] => 05440709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Apparatus and method for an improved content addressable memory using a random access memory to generate match information' [patent_app_type] => 1 [patent_app_number] => 8/203177 [patent_app_country] => US [patent_app_date] => 1994-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6983 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440709.pdf [firstpage_image] =>[orig_patent_app_number] => 203177 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/203177
Apparatus and method for an improved content addressable memory using a random access memory to generate match information Feb 27, 1994 Issued
Array ( [id] => 3601152 [patent_doc_number] => 05551005 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches' [patent_app_type] => 1 [patent_app_number] => 8/201854 [patent_app_country] => US [patent_app_date] => 1994-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7330 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/551/05551005.pdf [firstpage_image] =>[orig_patent_app_number] => 201854 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/201854
Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches Feb 24, 1994 Issued
Array ( [id] => 3694556 [patent_doc_number] => 05634037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Multiprocessor system having a shared memory with exclusive access for a requesting processor which is maintained until normal completion of a process and for retrying the process when not normally completed' [patent_app_type] => 1 [patent_app_number] => 8/200964 [patent_app_country] => US [patent_app_date] => 1994-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5964 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/634/05634037.pdf [firstpage_image] =>[orig_patent_app_number] => 200964 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/200964
Multiprocessor system having a shared memory with exclusive access for a requesting processor which is maintained until normal completion of a process and for retrying the process when not normally completed Feb 23, 1994 Issued
Array ( [id] => 3616535 [patent_doc_number] => 05579500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Control apparatus for controlling data read accesses to memory and subsequent address generation scheme based on data/memory width determination and address validation' [patent_app_type] => 1 [patent_app_number] => 8/200217 [patent_app_country] => US [patent_app_date] => 1994-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 5673 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/579/05579500.pdf [firstpage_image] =>[orig_patent_app_number] => 200217 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/200217
Control apparatus for controlling data read accesses to memory and subsequent address generation scheme based on data/memory width determination and address validation Feb 22, 1994 Issued
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