Matthew M. Kim

Array ( [id] => 3604643 [patent_doc_number] => 05568635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Physical memory allocation system, program execution scheduling system, and information processor' [patent_app_type] => 1 [patent_app_number] => 8/200489 [patent_app_country] => US [patent_app_date] => 1994-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5479 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568635.pdf [firstpage_image] =>[orig_patent_app_number] => 200489 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3612254 [patent_doc_number] => 05559981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Pseudo static mask option register and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/194900 [patent_app_country] => US [patent_app_date] => 1994-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6180 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559981.pdf [firstpage_image] =>[orig_patent_app_number] => 194900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3544245 [patent_doc_number] => 05584007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Apparatus and method for discriminating among data to be stored in cache' [patent_app_type] => 1 [patent_app_number] => 8/194104 [patent_app_country] => US [patent_app_date] => 1994-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 10060 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/584/05584007.pdf [firstpage_image] =>[orig_patent_app_number] => 194104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3518665 [patent_doc_number] => 05515521 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Circuit and method for reducing delays associated with contention interference between code fetches and operand accesses of a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/193287 [patent_app_country] => US [patent_app_date] => 1994-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9929 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/515/05515521.pdf [firstpage_image] =>[orig_patent_app_number] => 193287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3420037 [patent_doc_number] => 05438665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-01 [patent_title] => 'Direct memory access controller for handling cyclic execution of data transfer in accordance with stored transfer control information' [patent_app_type] => 1 [patent_app_number] => 8/194871 [patent_app_country] => US [patent_app_date] => 1994-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4788 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/438/05438665.pdf [firstpage_image] =>[orig_patent_app_number] => 194871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3603478 [patent_doc_number] => 05586279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Data processing system and method for testing a data processor having a cache memory' [patent_app_type] => 1 [patent_app_number] => 8/187885 [patent_app_country] => US [patent_app_date] => 1994-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3038 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586279.pdf [firstpage_image] =>[orig_patent_app_number] => 187885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3503267 [patent_doc_number] => 05561780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'Method and apparatus for combining uncacheable write data into cache-line-sized write buffers' [patent_app_type] => 1 [patent_app_number] => 8/176395 [patent_app_country] => US [patent_app_date] => 1993-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6950 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561780.pdf [firstpage_image] =>[orig_patent_app_number] => 176395 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3566489 [patent_doc_number] => 05519846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Multiprocessor system with scheme for managing allocation and reservation of cache segments in a cache system employing round-robin replacement and exclusive access' [patent_app_type] => 1 [patent_app_number] => 8/172529 [patent_app_country] => US [patent_app_date] => 1993-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3924 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/519/05519846.pdf [firstpage_image] =>[orig_patent_app_number] => 172529 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3604546 [patent_doc_number] => 05568628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Storage control method and apparatus for highly reliable storage controller with multiple cache memories' [patent_app_type] => 1 [patent_app_number] => 8/165989 [patent_app_country] => US [patent_app_date] => 1993-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 14191 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568628.pdf [firstpage_image] =>[orig_patent_app_number] => 165989 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3028515 [patent_doc_number] => 05341494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Memory accessing system with an interface and memory selection unit utilizing write protect and strobe signals' [patent_app_type] => 1 [patent_app_number] => 8/165514 [patent_app_country] => US [patent_app_date] => 1993-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 11845 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 439 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341494.pdf [firstpage_image] =>[orig_patent_app_number] => 165514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3566474 [patent_doc_number] => 05519845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Method and system for storage and retrieval of iterative data associated with an iterative process within a cache' [patent_app_type] => 1 [patent_app_number] => 8/160019 [patent_app_country] => US [patent_app_date] => 1993-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4615 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/519/05519845.pdf [firstpage_image] =>[orig_patent_app_number] => 160019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3454276 [patent_doc_number] => 05430858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Method for RAM conservation employing a RAM disk area non-sequential addresses on arranged order basis to access executable procedures' [patent_app_type] => 1 [patent_app_number] => 8/158129 [patent_app_country] => US [patent_app_date] => 1993-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2001 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430858.pdf [firstpage_image] =>[orig_patent_app_number] => 158129 [rel_patent_id] =>[rel_patent_doc_number] =>)