Matthew M. Nelson

Array ( [id] => 8996545 [patent_doc_number] => 08520442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Method of operating semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/769537 [patent_app_country] => US [patent_app_date] => 2013-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4234 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13769537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9010925 [patent_doc_number] => 08526236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Programming methods for a memory device' [patent_app_type] => utility [patent_app_number] => 13/614223 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13614223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8287392 [patent_doc_number] => 20120175718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'BIPOLAR SELECT DEVICE FOR RESISTIVE SENSE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/422219 [patent_app_country] => US [patent_app_date] => 2012-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3546 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13422219 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8287392 [patent_doc_number] => 20120175718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'BIPOLAR SELECT DEVICE FOR RESISTIVE SENSE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/422219 [patent_app_country] => US [patent_app_date] => 2012-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3546 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13422219 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9089327 [patent_doc_number] => 08560774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Redundant solid state disk system via interconnect cards' [patent_app_type] => utility [patent_app_number] => 13/405056 [patent_app_country] => US [patent_app_date] => 2012-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5022 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13405056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8226355 [patent_doc_number] => 20120140559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'SELECTIVE MEMORY CELL PROGRAM AND ERASE' [patent_app_type] => utility [patent_app_number] => 13/397428 [patent_app_country] => US [patent_app_date] => 2012-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13397428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8225304 [patent_doc_number] => 20120139508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/370854 [patent_app_country] => US [patent_app_date] => 2012-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6782 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13370854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8195333 [patent_doc_number] => 20120120724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'PHASE CHANGE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/358994 [patent_app_country] => US [patent_app_date] => 2012-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10230 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20120120724.pdf [firstpage_image] =>[orig_patent_app_number] => 13358994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8803608 [patent_doc_number] => 08441887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Decoding circuit withstanding high voltage via low-voltage MOS transistor and the implementing method thereof' [patent_app_type] => utility [patent_app_number] => 13/338343 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4341 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13338343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8307188 [patent_doc_number] => 08228729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-24 [patent_title] => 'Structure and method for shuffling data within non-volatile memory devices' [patent_app_type] => utility [patent_app_number] => 13/333494 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 43 [patent_no_of_words] => 15205 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7730115 [patent_doc_number] => 20120014163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/179839 [patent_app_country] => US [patent_app_date] => 2011-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9443 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20120014163.pdf [firstpage_image] =>[orig_patent_app_number] => 13179839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8341576 [patent_doc_number] => 08243499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating' [patent_app_type] => utility [patent_app_number] => 13/116924 [patent_app_country] => US [patent_app_date] => 2011-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 16039 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13116924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7697971 [patent_doc_number] => 20110228619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'MEMORY CONTROL APPARATUS AND MASK TIMING ADJUSTING METHOD' [patent_app_type] => utility [patent_app_number] => 13/049695 [patent_app_country] => US [patent_app_date] => 2011-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6905 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20110228619.pdf [firstpage_image] =>[orig_patent_app_number] => 13049695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6044857 [patent_doc_number] => 20110205824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'Data processing system' [patent_app_type] => utility [patent_app_number] => 12/929899 [patent_app_country] => US [patent_app_date] => 2011-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20110205824.pdf [firstpage_image] =>[orig_patent_app_number] => 12929899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9010934 [patent_doc_number] => 08526245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Method and apparatus for managing open blocks in nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 13/027439 [patent_app_country] => US [patent_app_date] => 2011-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7185 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13027439 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8702717 [patent_doc_number] => 08395944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Method of operating semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/982529 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4208 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12982529 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8897998 [patent_doc_number] => 08477524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Nonvolatile memory devices and related methods and systems' [patent_app_type] => utility [patent_app_number] => 12/974809 [patent_app_country] => US [patent_app_date] => 2010-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12074 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12974809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8092739 [patent_doc_number] => 20120081981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'NONVOLATILE MEMORY APPARATUS WITH CHANGEABLE OPERATION SPEED AND RELATED SIGNAL CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 12/968085 [patent_app_country] => US [patent_app_date] => 2010-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4003 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20120081981.pdf [firstpage_image] =>[orig_patent_app_number] => 12968085 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7719116 [patent_doc_number] => 20120008451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/914319 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6736 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20120008451.pdf [firstpage_image] =>[orig_patent_app_number] => 12914319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8579287 [patent_doc_number] => 08345507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Storage device, substrate, liquid container, system and control method of storage device' [patent_app_type] => utility [patent_app_number] => 12/892093 [patent_app_country] => US [patent_app_date] => 2010-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 15298 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12892093 [rel_patent_id] =>[rel_patent_doc_number] =>)