Matthew O Savage

Array ( [id] => 3124682 [patent_doc_number] => 05396452 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 8/086222 [patent_app_country] => US [patent_app_date] => 1993-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 33 [patent_no_of_words] => 7623 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396452.pdf [firstpage_image] =>[orig_patent_app_number] => 086222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3499723 [patent_doc_number] => 05440510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Integrated circuit entirely protected against ultraviolet rays' [patent_app_type] => 1 [patent_app_number] => 8/086342 [patent_app_country] => US [patent_app_date] => 1993-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3320 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440510.pdf [firstpage_image] =>[orig_patent_app_number] => 086342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3491605 [patent_doc_number] => 05406527 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'Partial write transferable multiport memory' [patent_app_type] => 1 [patent_app_number] => 8/081175 [patent_app_country] => US [patent_app_date] => 1993-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2522 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/406/05406527.pdf [firstpage_image] =>[orig_patent_app_number] => 081175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3130714 [patent_doc_number] => 05381373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'Voltage stress test circuit for a DRAM' [patent_app_type] => 1 [patent_app_number] => 8/075313 [patent_app_country] => US [patent_app_date] => 1993-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 11344 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/381/05381373.pdf [firstpage_image] =>[orig_patent_app_number] => 075313 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3122881 [patent_doc_number] => 05414663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'VLSI memory with an improved sense amplifier with dummy bit lines for modeling addressable bit lines' [patent_app_type] => 1 [patent_app_number] => 8/071892 [patent_app_country] => US [patent_app_date] => 1993-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 35 [patent_no_of_words] => 22409 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414663.pdf [firstpage_image] =>[orig_patent_app_number] => 071892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3006541 [patent_doc_number] => 05363328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-08 [patent_title] => 'Highly stable asymmetric SRAM cell' [patent_app_type] => 1 [patent_app_number] => 8/069325 [patent_app_country] => US [patent_app_date] => 1993-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3698 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/363/05363328.pdf [firstpage_image] =>[orig_patent_app_number] => 069325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3080046 [patent_doc_number] => 05361230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-01 [patent_title] => 'Memory device delaying timing of outputting data in a test mode as compared with a normal operating mode' [patent_app_type] => 1 [patent_app_number] => 8/068709 [patent_app_country] => US [patent_app_date] => 1993-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4500 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/361/05361230.pdf [firstpage_image] =>[orig_patent_app_number] => 068709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3458192 [patent_doc_number] => 05386391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Semiconductor memory device, operating synchronously with a clock signal' [patent_app_type] => 1 [patent_app_number] => 8/068705 [patent_app_country] => US [patent_app_date] => 1993-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 54 [patent_no_of_words] => 15263 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386391.pdf [firstpage_image] =>[orig_patent_app_number] => 068705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3451557 [patent_doc_number] => 05398207 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-14 [patent_title] => 'MOS random access memory device with an internal voltage-down converting transistor' [patent_app_type] => 1 [patent_app_number] => 8/067629 [patent_app_country] => US [patent_app_date] => 1993-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5096 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/398/05398207.pdf [firstpage_image] =>[orig_patent_app_number] => 067629 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3527224 [patent_doc_number] => 05506814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Video random access memory device and method implementing independent two WE nibble control' [patent_app_type] => 1 [patent_app_number] => 8/069967 [patent_app_country] => US [patent_app_date] => 1993-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3104 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506814.pdf [firstpage_image] =>[orig_patent_app_number] => 069967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3085896 [patent_doc_number] => 05323341 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-21 [patent_title] => 'Method of interchangeably using dip memory devices in a single socket' [patent_app_type] => 1 [patent_app_number] => 8/067639 [patent_app_country] => US [patent_app_date] => 1993-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3033 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/323/05323341.pdf [firstpage_image] =>[orig_patent_app_number] => 067639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3012611 [patent_doc_number] => 05371705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Internal voltage generator for a non-volatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/066300 [patent_app_country] => US [patent_app_date] => 1993-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 20362 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371705.pdf [firstpage_image] =>[orig_patent_app_number] => 066300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3451481 [patent_doc_number] => 05398202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-14 [patent_title] => 'Reprogrammable nonvolatile semiconductor memory formed of MOS transistors and reprogramming method thereof' [patent_app_type] => 1 [patent_app_number] => 8/062397 [patent_app_country] => US [patent_app_date] => 1993-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4960 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/398/05398202.pdf [firstpage_image] =>[orig_patent_app_number] => 062397 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3462975 [patent_doc_number] => 05379251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Method and apparatus for static RAM' [patent_app_type] => 1 [patent_app_number] => 8/060544 [patent_app_country] => US [patent_app_date] => 1993-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 3645 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379251.pdf [firstpage_image] =>[orig_patent_app_number] => 060544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3114999 [patent_doc_number] => 05418640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-23 [patent_title] => 'Spatially graded optical switch' [patent_app_type] => 1 [patent_app_number] => 8/055346 [patent_app_country] => US [patent_app_date] => 1993-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2066 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/418/05418640.pdf [firstpage_image] =>[orig_patent_app_number] => 055346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3067905 [patent_doc_number] => 05339277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Address buffer' [patent_app_type] => 1 [patent_app_number] => 8/056078 [patent_app_country] => US [patent_app_date] => 1993-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2343 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/339/05339277.pdf [firstpage_image] =>[orig_patent_app_number] => 056078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3025559 [patent_doc_number] => 05341336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Method for stress testing decoders and periphery circuits' [patent_app_type] => 1 [patent_app_number] => 8/056376 [patent_app_country] => US [patent_app_date] => 1993-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2573 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341336.pdf [firstpage_image] =>[orig_patent_app_number] => 056376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3126421 [patent_doc_number] => 05450233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-12 [patent_title] => 'Microscope having Y-shaped frame structure' [patent_app_type] => 1 [patent_app_number] => 8/053877 [patent_app_country] => US [patent_app_date] => 1993-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 6282 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/450/05450233.pdf [firstpage_image] =>[orig_patent_app_number] => 053877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3082268 [patent_doc_number] => 05365375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-15 [patent_title] => 'External optical device for providing multiple optical ports for a gunsight' [patent_app_type] => 1 [patent_app_number] => 8/048002 [patent_app_country] => US [patent_app_date] => 1993-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2714 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/365/05365375.pdf [firstpage_image] =>[orig_patent_app_number] => 048002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3429078 [patent_doc_number] => 05390047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Stereoviewer and package' [patent_app_type] => 1 [patent_app_number] => 8/046806 [patent_app_country] => US [patent_app_date] => 1993-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2163 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/390/05390047.pdf [firstpage_image] =>[orig_patent_app_number] => 046806 [rel_patent_id] =>[rel_patent_doc_number] =>)