Search

Matthew O Savage

Examiner (ID: 1392, Phone: (571)272-1146 , Office: P/1773 )

Most Active Art Unit
1306
Art Unit(s)
1778, 1724, 1306, 1723, 1797, 1773, 1776
Total Applications
2718
Issued Applications
1844
Pending Applications
157
Abandoned Applications
717

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3703286 [patent_doc_number] => 05650966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Temperature compensated reference for overerase correction circuitry in a flash memory' [patent_app_type] => 1 [patent_app_number] => 8/551422 [patent_app_country] => US [patent_app_date] => 1995-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2808 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/650/05650966.pdf [firstpage_image] =>[orig_patent_app_number] => 551422 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/551422
Temperature compensated reference for overerase correction circuitry in a flash memory Oct 31, 1995 Issued
Array ( [id] => 3712695 [patent_doc_number] => 05646896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Memory device with reduced number of fuses' [patent_app_type] => 1 [patent_app_number] => 8/550587 [patent_app_country] => US [patent_app_date] => 1995-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4654 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646896.pdf [firstpage_image] =>[orig_patent_app_number] => 550587 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/550587
Memory device with reduced number of fuses Oct 30, 1995 Issued
Array ( [id] => 3657766 [patent_doc_number] => 05638316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-10 [patent_title] => 'Memory apparatus' [patent_app_type] => 1 [patent_app_number] => 8/550989 [patent_app_country] => US [patent_app_date] => 1995-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3040 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/638/05638316.pdf [firstpage_image] =>[orig_patent_app_number] => 550989 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/550989
Memory apparatus Oct 30, 1995 Issued
Array ( [id] => 3727811 [patent_doc_number] => 05617370 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Semiconductor memory device with controllable charging characteristics of column lines' [patent_app_type] => 1 [patent_app_number] => 8/549388 [patent_app_country] => US [patent_app_date] => 1995-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5225 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617370.pdf [firstpage_image] =>[orig_patent_app_number] => 549388 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/549388
Semiconductor memory device with controllable charging characteristics of column lines Oct 26, 1995 Issued
Array ( [id] => 3704753 [patent_doc_number] => 05596542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Semiconductor memory device having dual word line configuration' [patent_app_type] => 1 [patent_app_number] => 8/536189 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4356 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596542.pdf [firstpage_image] =>[orig_patent_app_number] => 536189 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/536189
Semiconductor memory device having dual word line configuration Sep 28, 1995 Issued
Array ( [id] => 3727782 [patent_doc_number] => 05617368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Semiconductor memory device equipped with serial data reading circuit and method of outputting serial data from semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/533788 [patent_app_country] => US [patent_app_date] => 1995-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 7432 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617368.pdf [firstpage_image] =>[orig_patent_app_number] => 533788 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/533788
Semiconductor memory device equipped with serial data reading circuit and method of outputting serial data from semiconductor memory Sep 25, 1995 Issued
Array ( [id] => 3516533 [patent_doc_number] => 05570319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-29 [patent_title] => 'Embedded access trees for memory arrays' [patent_app_type] => 1 [patent_app_number] => 8/522061 [patent_app_country] => US [patent_app_date] => 1995-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5061 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/570/05570319.pdf [firstpage_image] =>[orig_patent_app_number] => 522061 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/522061
Embedded access trees for memory arrays Aug 30, 1995 Issued
Array ( [id] => 3666943 [patent_doc_number] => 05659515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Semiconductor memory device capable of refresh operation in burst mode' [patent_app_type] => 1 [patent_app_number] => 8/520190 [patent_app_country] => US [patent_app_date] => 1995-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 30 [patent_no_of_words] => 11026 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659515.pdf [firstpage_image] =>[orig_patent_app_number] => 520190 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/520190
Semiconductor memory device capable of refresh operation in burst mode Aug 27, 1995 Issued
Array ( [id] => 3630500 [patent_doc_number] => 05615154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Flash memory device having erase verification' [patent_app_type] => 1 [patent_app_number] => 8/518688 [patent_app_country] => US [patent_app_date] => 1995-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 47 [patent_no_of_words] => 11369 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/615/05615154.pdf [firstpage_image] =>[orig_patent_app_number] => 518688 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/518688
Flash memory device having erase verification Aug 23, 1995 Issued
Array ( [id] => 3704522 [patent_doc_number] => 05596526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Non-volatile memory system of multi-level transistor cells and methods using same' [patent_app_type] => 1 [patent_app_number] => 8/515188 [patent_app_country] => US [patent_app_date] => 1995-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8520 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596526.pdf [firstpage_image] =>[orig_patent_app_number] => 515188 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/515188
Non-volatile memory system of multi-level transistor cells and methods using same Aug 14, 1995 Issued
Array ( [id] => 3541323 [patent_doc_number] => 05583821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage' [patent_app_type] => 1 [patent_app_number] => 8/509599 [patent_app_country] => US [patent_app_date] => 1995-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4560 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583821.pdf [firstpage_image] =>[orig_patent_app_number] => 509599 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/509599
Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage Jul 30, 1995 Issued
Array ( [id] => 3591938 [patent_doc_number] => 05581503 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein' [patent_app_type] => 1 [patent_app_number] => 8/520721 [patent_app_country] => US [patent_app_date] => 1995-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 80 [patent_no_of_words] => 31563 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581503.pdf [firstpage_image] =>[orig_patent_app_number] => 520721 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/520721
Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein Jul 30, 1995 Issued
Array ( [id] => 3699090 [patent_doc_number] => 05604700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Non-volatile memory cell having a single polysilicon gate' [patent_app_type] => 1 [patent_app_number] => 8/506989 [patent_app_country] => US [patent_app_date] => 1995-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3403 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604700.pdf [firstpage_image] =>[orig_patent_app_number] => 506989 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/506989
Non-volatile memory cell having a single polysilicon gate Jul 27, 1995 Issued
Array ( [id] => 3727452 [patent_doc_number] => 05617348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Low power data translation circuit and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/506305 [patent_app_country] => US [patent_app_date] => 1995-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5196 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617348.pdf [firstpage_image] =>[orig_patent_app_number] => 506305 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/506305
Low power data translation circuit and method of operation Jul 23, 1995 Issued
Array ( [id] => 3622856 [patent_doc_number] => 05566131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Memory circuit for display apparatus' [patent_app_type] => 1 [patent_app_number] => 8/504806 [patent_app_country] => US [patent_app_date] => 1995-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2139 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/566/05566131.pdf [firstpage_image] =>[orig_patent_app_number] => 504806 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/504806
Memory circuit for display apparatus Jul 18, 1995 Issued
Array ( [id] => 3657861 [patent_doc_number] => 05638322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-10 [patent_title] => 'Apparatus and method for improving common mode noise rejection in pseudo-differential sense amplifiers' [patent_app_type] => 1 [patent_app_number] => 8/503988 [patent_app_country] => US [patent_app_date] => 1995-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6726 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/638/05638322.pdf [firstpage_image] =>[orig_patent_app_number] => 503988 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/503988
Apparatus and method for improving common mode noise rejection in pseudo-differential sense amplifiers Jul 18, 1995 Issued
Array ( [id] => 3636606 [patent_doc_number] => 05621695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'SRAM with simplified architecture for use with pipelined data' [patent_app_type] => 1 [patent_app_number] => 8/502974 [patent_app_country] => US [patent_app_date] => 1995-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 3594 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/621/05621695.pdf [firstpage_image] =>[orig_patent_app_number] => 502974 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/502974
SRAM with simplified architecture for use with pipelined data Jul 16, 1995 Issued
Array ( [id] => 3519022 [patent_doc_number] => 05587953 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'First-in-first-out buffer memory' [patent_app_type] => 1 [patent_app_number] => 8/499087 [patent_app_country] => US [patent_app_date] => 1995-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3628 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/587/05587953.pdf [firstpage_image] =>[orig_patent_app_number] => 499087 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/499087
First-in-first-out buffer memory Jul 5, 1995 Issued
Array ( [id] => 3591890 [patent_doc_number] => 05581500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Memory cell with power supply induced reversed-bias pass transistors for reducing off-leakage current' [patent_app_type] => 1 [patent_app_number] => 8/498192 [patent_app_country] => US [patent_app_date] => 1995-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4069 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581500.pdf [firstpage_image] =>[orig_patent_app_number] => 498192 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/498192
Memory cell with power supply induced reversed-bias pass transistors for reducing off-leakage current Jul 4, 1995 Issued
Array ( [id] => 3608712 [patent_doc_number] => 05559747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Static RAM and processing apparatus including static RAM' [patent_app_type] => 1 [patent_app_number] => 8/496184 [patent_app_country] => US [patent_app_date] => 1995-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8623 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559747.pdf [firstpage_image] =>[orig_patent_app_number] => 496184 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/496184
Static RAM and processing apparatus including static RAM Jun 27, 1995 Issued
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