![](/images/general/no_picture/200_user.png)
Matthew O Savage
Examiner (ID: 1392, Phone: (571)272-1146 , Office: P/1773 )
Most Active Art Unit | 1306 |
Art Unit(s) | 1778, 1724, 1306, 1723, 1797, 1773, 1776 |
Total Applications | 2718 |
Issued Applications | 1844 |
Pending Applications | 157 |
Abandoned Applications | 717 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3866911
[patent_doc_number] => 05768194
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-16
[patent_title] => 'Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein'
[patent_app_type] => 1
[patent_app_number] => 8/473114
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 64
[patent_figures_cnt] => 80
[patent_no_of_words] => 31542
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/768/05768194.pdf
[firstpage_image] =>[orig_patent_app_number] => 473114
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/473114 | Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein | Jun 6, 1995 | Issued |
Array
(
[id] => 3613078
[patent_doc_number] => 05579274
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Sense circuit for a flash eefprom cell having a negative delta threshold voltage'
[patent_app_type] => 1
[patent_app_number] => 8/483038
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 11517
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[patent_maintenance] => 1
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[pdf_file] => patents/05/579/05579274.pdf
[firstpage_image] =>[orig_patent_app_number] => 483038
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/483038 | Sense circuit for a flash eefprom cell having a negative delta threshold voltage | Jun 5, 1995 | Issued |
Array
(
[id] => 3565948
[patent_doc_number] => 05544102
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-06
[patent_title] => 'Semiconductor memory device including stabilizing capacitive elements each having a MOS capacitor structure'
[patent_app_type] => 1
[patent_app_number] => 8/471047
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[pdf_file] => patents/05/544/05544102.pdf
[firstpage_image] =>[orig_patent_app_number] => 471047
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/471047 | Semiconductor memory device including stabilizing capacitive elements each having a MOS capacitor structure | Jun 5, 1995 | Issued |
Array
(
[id] => 3740932
[patent_doc_number] => 05666311
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-09
[patent_title] => 'Method of making semiconductor device having isolating trenches'
[patent_app_type] => 1
[patent_app_number] => 8/467834
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
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[patent_no_of_words] => 7603
[patent_no_of_claims] => 45
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[pdf_file] => patents/05/666/05666311.pdf
[firstpage_image] =>[orig_patent_app_number] => 467834
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/467834 | Method of making semiconductor device having isolating trenches | Jun 5, 1995 | Issued |
Array
(
[id] => 3705376
[patent_doc_number] => 05619470
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-08
[patent_title] => 'Non-volatile dynamic random access memory'
[patent_app_type] => 1
[patent_app_number] => 8/459098
[patent_app_country] => US
[patent_app_date] => 1995-06-02
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[pdf_file] => patents/05/619/05619470.pdf
[firstpage_image] =>[orig_patent_app_number] => 459098
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/459098 | Non-volatile dynamic random access memory | Jun 1, 1995 | Issued |
Array
(
[id] => 3597682
[patent_doc_number] => 05550770
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-27
[patent_title] => 'Semiconductor memory device having ferroelectric capacitor memory cells with reading, writing and forced refreshing functions and a method of operating the same'
[patent_app_type] => 1
[patent_app_number] => 8/458159
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[pdf_file] => patents/05/550/05550770.pdf
[firstpage_image] =>[orig_patent_app_number] => 458159
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/458159 | Semiconductor memory device having ferroelectric capacitor memory cells with reading, writing and forced refreshing functions and a method of operating the same | Jun 1, 1995 | Issued |
Array
(
[id] => 3738575
[patent_doc_number] => 05671186
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-23
[patent_title] => 'Semiconductor memory device having bit line precharger'
[patent_app_type] => 1
[patent_app_number] => 8/457588
[patent_app_country] => US
[patent_app_date] => 1995-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3240
[patent_no_of_claims] => 18
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[pdf_file] => patents/05/671/05671186.pdf
[firstpage_image] =>[orig_patent_app_number] => 457588
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/457588 | Semiconductor memory device having bit line precharger | May 31, 1995 | Issued |
Array
(
[id] => 3559447
[patent_doc_number] => 05548552
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-20
[patent_title] => 'Reconfigurable programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 8/457884
[patent_app_country] => US
[patent_app_date] => 1995-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5172
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[pdf_file] => patents/05/548/05548552.pdf
[firstpage_image] =>[orig_patent_app_number] => 457884
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/457884 | Reconfigurable programmable logic device | May 30, 1995 | Issued |
Array
(
[id] => 3741208
[patent_doc_number] => 05636164
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-03
[patent_title] => 'Gate array for accelerating access to a random access memory'
[patent_app_type] => 1
[patent_app_number] => 8/448083
[patent_app_country] => US
[patent_app_date] => 1995-05-23
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[pdf_file] => patents/05/636/05636164.pdf
[firstpage_image] =>[orig_patent_app_number] => 448083
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/448083 | Gate array for accelerating access to a random access memory | May 22, 1995 | Issued |
Array
(
[id] => 3608728
[patent_doc_number] => 05559748
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-24
[patent_title] => 'Semiconductor integrated circuit allowing change of product specification and chip screening method therewith'
[patent_app_type] => 1
[patent_app_number] => 8/438656
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[patent_app_date] => 1995-05-09
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[pdf_file] => patents/05/559/05559748.pdf
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Array
(
[id] => 3691352
[patent_doc_number] => 05633827
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-27
[patent_title] => 'Semiconductor integrated circuit device allowing change of product specification and chip screening method therewith'
[patent_app_type] => 1
[patent_app_number] => 8/435661
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[pdf_file] => patents/05/633/05633827.pdf
[firstpage_image] =>[orig_patent_app_number] => 435661
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Array
(
[id] => 3668037
[patent_doc_number] => 05627788
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[patent_issue_date] => 1997-05-06
[patent_title] => 'Memory unit with bit line discharger'
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[patent_app_number] => 8/437090
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[firstpage_image] =>[orig_patent_app_number] => 437090
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/437090 | Memory unit with bit line discharger | May 4, 1995 | Issued |
Array
(
[id] => 3482404
[patent_doc_number] => 05477491
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-19
[patent_title] => 'Semiconductor memory device with a self-initializing circuit operable after supply of power'
[patent_app_type] => 1
[patent_app_number] => 8/431383
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[pdf_file] => patents/05/477/05477491.pdf
[firstpage_image] =>[orig_patent_app_number] => 431383
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/431383 | Semiconductor memory device with a self-initializing circuit operable after supply of power | Apr 27, 1995 | Issued |
Array
(
[id] => 3566959
[patent_doc_number] => 05502681
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[patent_kind] => NA
[patent_issue_date] => 1996-03-26
[patent_title] => 'Column start signal generation circuit for memory device'
[patent_app_type] => 1
[patent_app_number] => 8/428987
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 428987
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/428987 | Column start signal generation circuit for memory device | Apr 25, 1995 | Issued |
Array
(
[id] => 3613010
[patent_doc_number] => 05579270
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[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Flash EEPROM with auto-function for automatically writing or erasing data'
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[firstpage_image] =>[orig_patent_app_number] => 428696
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/428696 | Flash EEPROM with auto-function for automatically writing or erasing data | Apr 24, 1995 | Issued |
Array
(
[id] => 3712709
[patent_doc_number] => 05646897
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-08
[patent_title] => 'Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels'
[patent_app_type] => 1
[patent_app_number] => 8/426384
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[firstpage_image] =>[orig_patent_app_number] => 426384
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/426384 | Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels | Apr 20, 1995 | Issued |
Array
(
[id] => 3608553
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[patent_title] => 'Non-volatile semiconductor memory device capable of preventing excessive-writing'
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[firstpage_image] =>[orig_patent_app_number] => 424646
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/424646 | Non-volatile semiconductor memory device capable of preventing excessive-writing | Apr 18, 1995 | Issued |
Array
(
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Array
(
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[firstpage_image] =>[orig_patent_app_number] => 421938
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/421938 | Apparatus for and method of facilitating proper data transfer between two or more digital memory elements | Apr 13, 1995 | Issued |
Array
(
[id] => 3636363
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[pdf_file] => patents/05/621/05621678.pdf
[firstpage_image] =>[orig_patent_app_number] => 422237
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/422237 | Programmable memory controller for power and noise reduction | Apr 12, 1995 | Issued |