Search

Matthew O Savage

Examiner (ID: 1392, Phone: (571)272-1146 , Office: P/1773 )

Most Active Art Unit
1306
Art Unit(s)
1778, 1724, 1306, 1723, 1797, 1773, 1776
Total Applications
2718
Issued Applications
1844
Pending Applications
157
Abandoned Applications
717

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3618016 [patent_doc_number] => 05590084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Semiconductor memory device having a column selector' [patent_app_type] => 1 [patent_app_number] => 8/419688 [patent_app_country] => US [patent_app_date] => 1995-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4468 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590084.pdf [firstpage_image] =>[orig_patent_app_number] => 419688 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/419688
Semiconductor memory device having a column selector Apr 10, 1995 Issued
Array ( [id] => 3674241 [patent_doc_number] => 05668759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Method for erasing and verifying nonvolatile semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/419897 [patent_app_country] => US [patent_app_date] => 1995-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 46 [patent_no_of_words] => 11425 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668759.pdf [firstpage_image] =>[orig_patent_app_number] => 419897 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/419897
Method for erasing and verifying nonvolatile semiconductor memory Apr 10, 1995 Issued
Array ( [id] => 3668135 [patent_doc_number] => 05627795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Timing generating device' [patent_app_type] => 1 [patent_app_number] => 8/418289 [patent_app_country] => US [patent_app_date] => 1995-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 9943 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627795.pdf [firstpage_image] =>[orig_patent_app_number] => 418289 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/418289
Timing generating device Apr 6, 1995 Issued
Array ( [id] => 3632853 [patent_doc_number] => 05594683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'SRAM cell using a CMOS compatible high gain gated lateral BJT' [patent_app_type] => 1 [patent_app_number] => 8/418485 [patent_app_country] => US [patent_app_date] => 1995-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2896 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594683.pdf [firstpage_image] =>[orig_patent_app_number] => 418485 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/418485
SRAM cell using a CMOS compatible high gain gated lateral BJT Apr 6, 1995 Issued
Array ( [id] => 3544675 [patent_doc_number] => 05557567 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'Method for programming an AMG EPROM or flash memory when cells of the array are formed to store multiple bits of data' [patent_app_type] => 1 [patent_app_number] => 8/417938 [patent_app_country] => US [patent_app_date] => 1995-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5296 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 428 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/557/05557567.pdf [firstpage_image] =>[orig_patent_app_number] => 417938 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/417938
Method for programming an AMG EPROM or flash memory when cells of the array are formed to store multiple bits of data Apr 5, 1995 Issued
Array ( [id] => 3633039 [patent_doc_number] => 05612924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Semiconductor memory device using internal voltage obtained by boosting supply voltage' [patent_app_type] => 1 [patent_app_number] => 8/417888 [patent_app_country] => US [patent_app_date] => 1995-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3919 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612924.pdf [firstpage_image] =>[orig_patent_app_number] => 417888 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/417888
Semiconductor memory device using internal voltage obtained by boosting supply voltage Apr 5, 1995 Issued
08/420943 DYNAMIC RANDOM-ACCESS MEMORY HAVING DECODING CIRCUITRY FOR PARTIAL ARRAY BLOCKS Apr 5, 1995 Abandoned
Array ( [id] => 3704728 [patent_doc_number] => 05596540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Serial to parallel and parallel to serial architecture for a RAM based FIFO memory' [patent_app_type] => 1 [patent_app_number] => 8/414252 [patent_app_country] => US [patent_app_date] => 1995-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6814 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596540.pdf [firstpage_image] =>[orig_patent_app_number] => 414252 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/414252
Serial to parallel and parallel to serial architecture for a RAM based FIFO memory Mar 30, 1995 Issued
Array ( [id] => 3521143 [patent_doc_number] => 05563844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Architecture for accessing very high density memory device' [patent_app_type] => 1 [patent_app_number] => 8/411983 [patent_app_country] => US [patent_app_date] => 1995-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5256 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/563/05563844.pdf [firstpage_image] =>[orig_patent_app_number] => 411983 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/411983
Architecture for accessing very high density memory device Mar 27, 1995 Issued
Array ( [id] => 3699170 [patent_doc_number] => 05604706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Data storage medium for storing data as a polarization of a data magnetic field and method and apparatus using spin-polarized electrons for storing the data onto the data storage medium and reading the stored data therefrom' [patent_app_type] => 1 [patent_app_number] => 8/408784 [patent_app_country] => US [patent_app_date] => 1995-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 7226 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604706.pdf [firstpage_image] =>[orig_patent_app_number] => 408784 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/408784
Data storage medium for storing data as a polarization of a data magnetic field and method and apparatus using spin-polarized electrons for storing the data onto the data storage medium and reading the stored data therefrom Mar 22, 1995 Issued
Array ( [id] => 3668065 [patent_doc_number] => 05627790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Reading circuit for an integrated semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/408589 [patent_app_country] => US [patent_app_date] => 1995-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1939 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627790.pdf [firstpage_image] =>[orig_patent_app_number] => 408589 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/408589
Reading circuit for an integrated semiconductor memory device Mar 21, 1995 Issued
Array ( [id] => 3727599 [patent_doc_number] => 05617358 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Nonvolatile semiconductor memory device capable of converging threshold voltage with low power supply voltage' [patent_app_type] => 1 [patent_app_number] => 8/402037 [patent_app_country] => US [patent_app_date] => 1995-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 4629 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617358.pdf [firstpage_image] =>[orig_patent_app_number] => 402037 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/402037
Nonvolatile semiconductor memory device capable of converging threshold voltage with low power supply voltage Mar 9, 1995 Issued
Array ( [id] => 3507733 [patent_doc_number] => 05532970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-02 [patent_title] => 'No latency pipeline' [patent_app_type] => 1 [patent_app_number] => 8/398334 [patent_app_country] => US [patent_app_date] => 1995-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2397 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/532/05532970.pdf [firstpage_image] =>[orig_patent_app_number] => 398334 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/398334
No latency pipeline Mar 2, 1995 Issued
Array ( [id] => 3669885 [patent_doc_number] => 05648927 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Differential amplifier in a memory data path' [patent_app_type] => 1 [patent_app_number] => 8/397006 [patent_app_country] => US [patent_app_date] => 1995-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4985 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/648/05648927.pdf [firstpage_image] =>[orig_patent_app_number] => 397006 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/397006
Differential amplifier in a memory data path Feb 28, 1995 Issued
Array ( [id] => 3523357 [patent_doc_number] => 05513137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Flash memory having transistor redundancy' [patent_app_type] => 1 [patent_app_number] => 8/393584 [patent_app_country] => US [patent_app_date] => 1995-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4119 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/513/05513137.pdf [firstpage_image] =>[orig_patent_app_number] => 393584 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/393584
Flash memory having transistor redundancy Feb 22, 1995 Issued
Array ( [id] => 3704536 [patent_doc_number] => 05596527 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Electrically alterable n-bit per cell non-volatile memory with reference cells' [patent_app_type] => 1 [patent_app_number] => 8/387562 [patent_app_country] => US [patent_app_date] => 1995-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4521 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 389 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596527.pdf [firstpage_image] =>[orig_patent_app_number] => 387562 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/387562
Electrically alterable n-bit per cell non-volatile memory with reference cells Feb 12, 1995 Issued
Array ( [id] => 3546723 [patent_doc_number] => 05495436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Anti-fuse ROM programming circuit' [patent_app_type] => 1 [patent_app_number] => 8/372087 [patent_app_country] => US [patent_app_date] => 1995-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4267 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495436.pdf [firstpage_image] =>[orig_patent_app_number] => 372087 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/372087
Anti-fuse ROM programming circuit Jan 12, 1995 Issued
Array ( [id] => 3562440 [patent_doc_number] => 05493527 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'High density ROM with select lines' [patent_app_type] => 1 [patent_app_number] => 8/370569 [patent_app_country] => US [patent_app_date] => 1995-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3393 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493527.pdf [firstpage_image] =>[orig_patent_app_number] => 370569 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/370569
High density ROM with select lines Jan 8, 1995 Issued
Array ( [id] => 3534639 [patent_doc_number] => 05504708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Flash EEPROM array with P-tank insulated from substrate by deep N-tank' [patent_app_type] => 1 [patent_app_number] => 8/369025 [patent_app_country] => US [patent_app_date] => 1995-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3523 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504708.pdf [firstpage_image] =>[orig_patent_app_number] => 369025 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/369025
Flash EEPROM array with P-tank insulated from substrate by deep N-tank Jan 4, 1995 Issued
Array ( [id] => 3659221 [patent_doc_number] => 05684748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Circuit for testing reliability of chip and semiconductor memory device having the circuit' [patent_app_type] => 1 [patent_app_number] => 8/366586 [patent_app_country] => US [patent_app_date] => 1994-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5451 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684748.pdf [firstpage_image] =>[orig_patent_app_number] => 366586 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/366586
Circuit for testing reliability of chip and semiconductor memory device having the circuit Dec 29, 1994 Issued
Menu