Search

Matthew P. Coughlin

Examiner (ID: 19098, Phone: (571)270-1311 , Office: P/1626 )

Most Active Art Unit
1626
Art Unit(s)
1626
Total Applications
1390
Issued Applications
919
Pending Applications
92
Abandoned Applications
408

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16722158 [patent_doc_number] => 20210089305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => INSTRUCTION EXECUTING METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 17/028352 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028352 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/028352
INSTRUCTION EXECUTING METHOD AND APPARATUS Sep 21, 2020 Abandoned
Array ( [id] => 17462319 [patent_doc_number] => 20220075624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => ALTERNATE PATH FOR BRANCH PREDICTION REDIRECT [patent_app_type] => utility [patent_app_number] => 17/012833 [patent_app_country] => US [patent_app_date] => 2020-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17012833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/012833
ALTERNATE PATH FOR BRANCH PREDICTION REDIRECT Sep 3, 2020 Abandoned
Array ( [id] => 17984571 [patent_doc_number] => 20220350608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => BRANCH PREDICTION CIRCUIT AND INSTRUCTION PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/761293 [patent_app_country] => US [patent_app_date] => 2020-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6041 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17761293 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/761293
BRANCH PREDICTION CIRCUIT AND INSTRUCTION PROCESSING METHOD Sep 1, 2020 Abandoned
Array ( [id] => 16514780 [patent_doc_number] => 20200394038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => LOOK UP TABLE WITH DATA ELEMENT PROMOTION [patent_app_type] => utility [patent_app_number] => 17/008456 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008456 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008456
Look up table with data element promotion Aug 30, 2020 Issued
Array ( [id] => 16508119 [patent_doc_number] => 20200387375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => INSTRUCTION DEMARCATOR [patent_app_type] => utility [patent_app_number] => 16/991408 [patent_app_country] => US [patent_app_date] => 2020-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16991408 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/991408
Instruction length based parallel instruction demarcator Aug 11, 2020 Issued
Array ( [id] => 16486339 [patent_doc_number] => 20200379945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => CIRCULAR RECONFIGURATION FOR RECONFIGURABLE PARALLEL PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/931546 [patent_app_country] => US [patent_app_date] => 2020-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16931546 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/931546
Circular reconfiguration for reconfigurable parallel processor using a plurality of memory ports coupled to a commonly accessible memory unit Jul 16, 2020 Issued
Array ( [id] => 16630473 [patent_doc_number] => 20210049126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => RECONFIGURABLE PARALLEL PROCESSING [patent_app_type] => utility [patent_app_number] => 16/932039 [patent_app_country] => US [patent_app_date] => 2020-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16932039 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/932039
Reconfigurable parallel processing with various reconfigurable units to form two or more physical data paths and routing data from one physical data path to a gasket memory to be used in a future physical data path as input Jul 16, 2020 Issued
Array ( [id] => 17238456 [patent_doc_number] => 11182336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Reconfigurable parallel processing with a temporary data storage coupled to a plurality of processing elements (PES) to store a PE execution result to be used by a PE during a next PE configuration [patent_app_type] => utility [patent_app_number] => 16/931993 [patent_app_country] => US [patent_app_date] => 2020-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 35 [patent_no_of_words] => 21844 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16931993 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/931993
Reconfigurable parallel processing with a temporary data storage coupled to a plurality of processing elements (PES) to store a PE execution result to be used by a PE during a next PE configuration Jul 16, 2020 Issued
Array ( [id] => 16486338 [patent_doc_number] => 20200379944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => Shared Memory Structure for Reconfigurable Parallel Processor [patent_app_type] => utility [patent_app_number] => 16/930472 [patent_app_country] => US [patent_app_date] => 2020-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16930472 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/930472
Shared memory access for reconfigurable parallel processor using a plurality of memory ports each comprising an address calculation unit Jul 15, 2020 Issued
Array ( [id] => 17316960 [patent_doc_number] => 20210406009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => APPARATUS FOR OPTIMIZED MICROCODE INSTRUCTIONS FOR DYNAMIC PROGRAMMING BASED ON IDEMPOTENT SEMIRING OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/917634 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917634 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917634
APPARATUS FOR OPTIMIZED MICROCODE INSTRUCTIONS FOR DYNAMIC PROGRAMMING BASED ON IDEMPOTENT SEMIRING OPERATIONS Jun 29, 2020 Abandoned
Array ( [id] => 17316958 [patent_doc_number] => 20210406007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => GENERATING OPTIMIZED MICROCODE INSTRUCTIONS FOR DYNAMIC PROGRAMMING BASED ON IDEMPOTENT SEMIRING OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/917654 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917654 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917654
GENERATING OPTIMIZED MICROCODE INSTRUCTIONS FOR DYNAMIC PROGRAMMING BASED ON IDEMPOTENT SEMIRING OPERATIONS Jun 29, 2020 Abandoned
Array ( [id] => 17238453 [patent_doc_number] => 11182333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Private memory access for reconfigurable parallel processor using a plurality of memory ports each comprising an address calculation unit [patent_app_type] => utility [patent_app_number] => 16/906352 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 19846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906352 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906352
Private memory access for reconfigurable parallel processor using a plurality of memory ports each comprising an address calculation unit Jun 18, 2020 Issued
Array ( [id] => 16787977 [patent_doc_number] => 10990410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Systems and methods for virtually partitioning a machine perception and dense algorithm integrated circuit [patent_app_type] => utility [patent_app_number] => 16/864896 [patent_app_country] => US [patent_app_date] => 2020-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16864896 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/864896
Systems and methods for virtually partitioning a machine perception and dense algorithm integrated circuit Apr 30, 2020 Issued
Array ( [id] => 18095515 [patent_doc_number] => 20220413856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => INSTRUCTION EXECUTION METHOD, APPARATUS AND DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/780809 [patent_app_country] => US [patent_app_date] => 2020-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7820 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17780809 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/780809
INSTRUCTION EXECUTION METHOD, APPARATUS AND DEVICE, AND STORAGE MEDIUM Apr 26, 2020 Abandoned
Array ( [id] => 17877330 [patent_doc_number] => 11449344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-20 [patent_title] => Regular expression processor and parallel processing architecture [patent_app_type] => utility [patent_app_number] => 16/854441 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 13146 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854441 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/854441
Regular expression processor and parallel processing architecture Apr 20, 2020 Issued
Array ( [id] => 17128540 [patent_doc_number] => 20210303309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => RECONSTRUCTION OF FLAGS AND DATA FOR IMMEDIATE FOLDING [patent_app_type] => utility [patent_app_number] => 16/833072 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833072 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/833072
RECONSTRUCTION OF FLAGS AND DATA FOR IMMEDIATE FOLDING Mar 26, 2020 Abandoned
Array ( [id] => 18873410 [patent_doc_number] => 11861220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Allocation of memory by mapping registers referenced by different instances of a task to individual logical memories [patent_app_type] => utility [patent_app_number] => 16/791323 [patent_app_country] => US [patent_app_date] => 2020-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 10105 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16791323 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/791323
Allocation of memory by mapping registers referenced by different instances of a task to individual logical memories Feb 13, 2020 Issued
Array ( [id] => 16409261 [patent_doc_number] => 10817820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Facilitating provisioning in a mixed environment of locales [patent_app_type] => utility [patent_app_number] => 16/786997 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3342 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786997 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/786997
Facilitating provisioning in a mixed environment of locales Feb 9, 2020 Issued
Array ( [id] => 16065029 [patent_doc_number] => 10691464 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-23 [patent_title] => Systems and methods for virtually partitioning a machine perception and dense algorithm integrated circuit [patent_app_type] => utility [patent_app_number] => 16/747976 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747976 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747976
Systems and methods for virtually partitioning a machine perception and dense algorithm integrated circuit Jan 20, 2020 Issued
Array ( [id] => 15902889 [patent_doc_number] => 20200150964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => LIVELOCK RECOVERY CIRCUIT FOR DETECTING ILLEGAL REPETITION OF AN INSTRUCTION AND TRANSITIONING TO A KNOWN STATE [patent_app_type] => utility [patent_app_number] => 16/743586 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743586 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/743586
Livelock recovery circuit for detecting illegal repetition of an instruction and transitioning to a known state Jan 14, 2020 Issued
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