Search

Matthew P. Coughlin

Examiner (ID: 19098, Phone: (571)270-1311 , Office: P/1626 )

Most Active Art Unit
1626
Art Unit(s)
1626
Total Applications
1390
Issued Applications
919
Pending Applications
92
Abandoned Applications
408

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14135607 [patent_doc_number] => 20190102193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => APPARATUS AND METHOD FOR COMPLEX BY COMPLEX CONJUGATE MULTIPLICATION [patent_app_type] => utility [patent_app_number] => 15/721448 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721448 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721448
Apparatus and method for complex by complex conjugate multiplication Sep 28, 2017 Issued
Array ( [id] => 16037075 [patent_doc_number] => 10680977 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-09 [patent_title] => Splitting data into an information vector and a control vector and processing, at a stage of a control pipeline, the control vector and a data block of the information vector extracted from a corresponding stage of a data pipeline [patent_app_type] => utility [patent_app_number] => 15/716367 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13637 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716367 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716367
Splitting data into an information vector and a control vector and processing, at a stage of a control pipeline, the control vector and a data block of the information vector extracted from a corresponding stage of a data pipeline Sep 25, 2017 Issued
Array ( [id] => 12120931 [patent_doc_number] => 20180004517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'APPARATUS AND METHOD FOR PROPAGATING CONDITIONALLY EVALUATED VALUES IN SIMD/VECTOR EXECUTION USING AN INPUT MASK REGISTER' [patent_app_type] => utility [patent_app_number] => 15/708016 [patent_app_country] => US [patent_app_date] => 2017-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14922 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15708016 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/708016
APPARATUS AND METHOD FOR PROPAGATING CONDITIONALLY EVALUATED VALUES IN SIMD/VECTOR EXECUTION USING AN INPUT MASK REGISTER Sep 17, 2017 Abandoned
Array ( [id] => 15670423 [patent_doc_number] => 10599441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Code sequencer that, in response to a primary processing unit encountering a trigger instruction, receives a thread identifier, executes predefined instruction sequences, and offloads computations to at least one accelerator [patent_app_type] => utility [patent_app_number] => 15/694893 [patent_app_country] => US [patent_app_date] => 2017-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3526 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694893 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694893
Code sequencer that, in response to a primary processing unit encountering a trigger instruction, receives a thread identifier, executes predefined instruction sequences, and offloads computations to at least one accelerator Sep 3, 2017 Issued
Array ( [id] => 16551586 [patent_doc_number] => 10884745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Providing a predicted target address to multiple locations based on detecting an affiliated relationship [patent_app_type] => utility [patent_app_number] => 15/680759 [patent_app_country] => US [patent_app_date] => 2017-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 34 [patent_no_of_words] => 19147 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680759 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/680759
Providing a predicted target address to multiple locations based on detecting an affiliated relationship Aug 17, 2017 Issued
Array ( [id] => 13708565 [patent_doc_number] => 20170365237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => Processing a Plurality of Threads of a Single Instruction Multiple Data Group [patent_app_type] => utility [patent_app_number] => 15/679316 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9749 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679316 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/679316
Processing a Plurality of Threads of a Single Instruction Multiple Data Group Aug 16, 2017 Abandoned
Array ( [id] => 15788873 [patent_doc_number] => 10628161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Processor for correlation-based infinite loop detection [patent_app_type] => utility [patent_app_number] => 15/662454 [patent_app_country] => US [patent_app_date] => 2017-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8896 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15662454 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/662454
Processor for correlation-based infinite loop detection Jul 27, 2017 Issued
Array ( [id] => 13707043 [patent_doc_number] => 20170364476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => INSTRUCTION AND LOGIC FOR PERFORMING A DOT-PRODUCT OPERATION [patent_app_type] => utility [patent_app_number] => 15/640395 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640395 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/640395
INSTRUCTION AND LOGIC FOR PERFORMING A DOT-PRODUCT OPERATION Jun 29, 2017 Abandoned
Array ( [id] => 15997839 [patent_doc_number] => 20200174790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => METHOD AND APPARATUS FOR VECTORIZING HISTOGRAM LOOPS [patent_app_type] => utility [patent_app_number] => 16/616385 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16616385 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/616385
METHOD AND APPARATUS FOR VECTORIZING HISTOGRAM LOOPS Jun 29, 2017 Abandoned
Array ( [id] => 13782517 [patent_doc_number] => 20190004797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => EXPOSING VALID BYTE LANES AS VECTOR PREDICATES TO CPU [patent_app_type] => utility [patent_app_number] => 15/635449 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -40 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15635449 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/635449
Exposing valid byte lanes as vector predicates to CPU Jun 27, 2017 Issued
Array ( [id] => 13782913 [patent_doc_number] => 20190004995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => High-Speed, Fixed-Function, Computer Accelerator [patent_app_type] => utility [patent_app_number] => 15/635864 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15635864 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/635864
Computer architecture with fixed program dataflow elements and stream processor Jun 27, 2017 Issued
Array ( [id] => 15284505 [patent_doc_number] => 10514916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => In-lane vector shuffle instructions [patent_app_type] => utility [patent_app_number] => 15/613809 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4892 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 405 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15613809 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/613809
In-lane vector shuffle instructions Jun 4, 2017 Issued
Array ( [id] => 11868294 [patent_doc_number] => 20170235579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'PROCESSOR FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTING AND RESTORING' [patent_app_type] => utility [patent_app_number] => 15/586636 [patent_app_country] => US [patent_app_date] => 2017-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 23192 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15586636 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/586636
PROCESSOR FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTING AND RESTORING May 3, 2017 Abandoned
Array ( [id] => 11868353 [patent_doc_number] => 20170235638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'SYSTEM-ON-CHIP FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTING AND RESTORING' [patent_app_type] => utility [patent_app_number] => 15/586898 [patent_app_country] => US [patent_app_date] => 2017-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 23171 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15586898 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/586898
SYSTEM-ON-CHIP FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTING AND RESTORING May 3, 2017 Abandoned
Array ( [id] => 11868295 [patent_doc_number] => 20170235580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'SYSTEM FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTING AND RESTORING' [patent_app_type] => utility [patent_app_number] => 15/586930 [patent_app_country] => US [patent_app_date] => 2017-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 23189 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15586930 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/586930
SYSTEM FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTING AND RESTORING May 3, 2017 Abandoned
Array ( [id] => 17454784 [patent_doc_number] => 11269643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values [patent_app_type] => utility [patent_app_number] => 15/482798 [patent_app_country] => US [patent_app_date] => 2017-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 43 [patent_no_of_words] => 33409 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15482798 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/482798
Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values Apr 8, 2017 Issued
Array ( [id] => 15349279 [patent_doc_number] => 20200012531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => EXECUTION UNIT-SHARED HYBRID TECHNIQUE FOR ACCELERATED COMPUTING ON GRAPHICS PROCESSORS [patent_app_type] => utility [patent_app_number] => 16/475911 [patent_app_country] => US [patent_app_date] => 2017-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16475911 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/475911
EXECUTION UNIT-SHARED HYBRID TECHNIQUE FOR ACCELERATED COMPUTING ON GRAPHICS PROCESSORS Mar 31, 2017 Abandoned
Array ( [id] => 11665191 [patent_doc_number] => 20170153911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'DISTRIBUTED TRANSACTIONS ON MOBILE DEVICES VIA A MESSAGING SERVICE PROVIDED BY A MOBILE NETWORK OPERATOR' [patent_app_type] => utility [patent_app_number] => 15/432192 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432192 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/432192
Distributed transactions on mobile devices via a messaging service provided by a mobile network operator Feb 13, 2017 Issued
Array ( [id] => 14766713 [patent_doc_number] => 10394753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Conditional operation in an internal processor of a memory device [patent_app_type] => utility [patent_app_number] => 15/395602 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6335 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395602 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/395602
Conditional operation in an internal processor of a memory device Dec 29, 2016 Issued
Array ( [id] => 16957867 [patent_doc_number] => 11061730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Efficient scheduling for hyper-threaded CPUs using memory monitoring [patent_app_type] => utility [patent_app_number] => 15/355747 [patent_app_country] => US [patent_app_date] => 2016-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4084 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15355747 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/355747
Efficient scheduling for hyper-threaded CPUs using memory monitoring Nov 17, 2016 Issued
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