Matthew P. Coughlin

Array ( [id] => 19686217 [patent_doc_number] => 20250004762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => BINARY CONVOLUTION INSTRUCTIONS FOR BINARY NEURAL NETWORK COMPUTATIONS [patent_app_type] => utility [patent_app_number] => 18/344091 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19660662 [patent_doc_number] => 20240427727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => HANDLING DYNAMIC TENSOR LENGTHS IN A RECONFIGURABLE PROCESSOR THAT INCLUDES MULTIPLE MEMORY UNITS [patent_app_type] => utility [patent_app_number] => 18/213598 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18213598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18819511 [patent_doc_number] => 20230393851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => PROCESSING SYSTEM WITH INTEGRATED DOMAIN SPECIFIC ACCELERATORS [patent_app_type] => utility [patent_app_number] => 18/212128 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18212128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18711379 [patent_doc_number] => 20230334008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => EXECUTION ENGINE FOR EXECUTING SINGLE ASSIGNMENT PROGRAMS WITH AFFINE DEPENDENCIES [patent_app_type] => utility [patent_app_number] => 18/211447 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19219876 [patent_doc_number] => 20240184580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => Tracking of Data Readiness for Load and Store Operations [patent_app_type] => utility [patent_app_number] => 18/328839 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19617376 [patent_doc_number] => 20240403056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => SHADER LAUNCH SCHEDULING OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/205699 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18205699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19514157 [patent_doc_number] => 20240345843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SYSTEMS AND METHODS FOR PROCESSING FORMATTED DATA IN COMPUTATIONAL STORAGE [patent_app_type] => utility [patent_app_number] => 18/328688 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19069436 [patent_doc_number] => 20240103862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => COMPUTING DEVICE AND COMPUTING METHOD [patent_app_type] => utility [patent_app_number] => 18/326202 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20215041 [patent_doc_number] => 12411694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Processor having adaptive pipeline with latency reduction logic that selectively executes instructions to reduce latency [patent_app_type] => utility [patent_app_number] => 18/314264 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314264 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20374071 [patent_doc_number] => 12481505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Managing speculative instruction execution using speculative id in a graphflow apparatus [patent_app_type] => utility [patent_app_number] => 18/312365 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 12423 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19917819 [patent_doc_number] => 12293189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Data value prediction and pre-alignment based on prefetched predicted memory access address [patent_app_type] => utility [patent_app_number] => 18/312059 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7006 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19122753 [patent_doc_number] => 11966742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Apparatuses, methods, and systems for instructions to request a history reset of a processor core [patent_app_type] => utility [patent_app_number] => 18/311810 [patent_app_country] => US [patent_app_date] => 2023-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 28482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18772773 [patent_doc_number] => 20230367599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => Vector Gather with a Narrow Datapath [patent_app_type] => utility [patent_app_number] => 18/141466 [patent_app_country] => US [patent_app_date] => 2023-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141466 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18741705 [patent_doc_number] => 20230350686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => LOGIC CIRCUIT AND METHOD FOR CHECKING AND UPDATING PROGRAM COUNTER VALUES IN PIPELINE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/139914 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18139914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18727863 [patent_doc_number] => 20230342156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => APPARATUSES AND METHODS FOR SPECULATIVE EXECUTION SIDE CHANNEL MITIGATION [patent_app_type] => utility [patent_app_number] => 18/138591 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19466328 [patent_doc_number] => 20240319998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => ON-CHIP AI COMPUTE HARDWARE ACCELERATION [patent_app_type] => utility [patent_app_number] => 18/187465 [patent_app_country] => US [patent_app_date] => 2023-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18187465 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19725784 [patent_doc_number] => 20250028535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => DECODING METHOD, PROCESSOR, CHIP, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/714604 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18714604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18614278 [patent_doc_number] => 20230281015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => Processing Device for Intermediate Value Scaling [patent_app_type] => utility [patent_app_number] => 18/175050 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18175050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19405619 [patent_doc_number] => 20240289130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => DATA PROCESSING APPARATUS WITH SELECTIVELY DELAYED TRANSMISSION OF OPERANDS [patent_app_type] => utility [patent_app_number] => 18/174207 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18174207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19391383 [patent_doc_number] => 20240281253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => COMPRESSING INSTRUCTIONS FOR MACHINE-LEARNING ACCELERATORS [patent_app_type] => utility [patent_app_number] => 18/172016 [patent_app_country] => US [patent_app_date] => 2023-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18172016 [rel_patent_id] =>[rel_patent_doc_number] =>)