Search

Matthew P. Coughlin

Examiner (ID: 19098, Phone: (571)270-1311 , Office: P/1626 )

Most Active Art Unit
1626
Art Unit(s)
1626
Total Applications
1390
Issued Applications
919
Pending Applications
92
Abandoned Applications
408

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17984570 [patent_doc_number] => 20220350607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => METHOD OF EXECUTING OPERATION, ELECTRONIC DEVICE, AND COMPUTER-READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/867859 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867859 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/867859
METHOD OF EXECUTING OPERATION, ELECTRONIC DEVICE, AND COMPUTER-READABLE STORAGE MEDIUM Jul 18, 2022 Abandoned
Array ( [id] => 18881278 [patent_doc_number] => 20240004647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => VECTOR PROCESSOR WITH VECTOR AND ELEMENT REDUCTION METHOD [patent_app_type] => utility [patent_app_number] => 17/855816 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855816 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/855816
VECTOR PROCESSOR WITH VECTOR AND ELEMENT REDUCTION METHOD Jun 30, 2022 Abandoned
Array ( [id] => 19703881 [patent_doc_number] => 12197917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Exit history based branch prediction [patent_app_type] => utility [patent_app_number] => 17/849994 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9016 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849994 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/849994
Exit history based branch prediction Jun 26, 2022 Issued
Array ( [id] => 18819513 [patent_doc_number] => 20230393853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => SELECTIVELY UPDATING BRANCH PREDICTORS FOR LOOPS EXECUTED FROM LOOP BUFFERS IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/832350 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832350 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/832350
Selectively updating branch predictors for loops executed from loop buffers in a processor Jun 2, 2022 Issued
Array ( [id] => 19062161 [patent_doc_number] => 11941397 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-26 [patent_title] => Machine instructions for decoding acceleration including fuse input instructions to fuse multiple JPEG data blocks together to take advantage of a full SIMD width of a processor [patent_app_type] => utility [patent_app_number] => 17/804796 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 15389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804796 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/804796
Machine instructions for decoding acceleration including fuse input instructions to fuse multiple JPEG data blocks together to take advantage of a full SIMD width of a processor May 30, 2022 Issued
Array ( [id] => 19251006 [patent_doc_number] => 20240201996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => IMPROVEMENTS IN AND RELATING TO ENCODING AND COMPUTATION ON DISTRIBUTIONS OF DATA [patent_app_type] => utility [patent_app_number] => 18/562398 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18562398 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/562398
IMPROVEMENTS IN AND RELATING TO ENCODING AND COMPUTATION ON DISTRIBUTIONS OF DATA May 26, 2022 Pending
Array ( [id] => 18226739 [patent_doc_number] => 20230065733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => CALCULATOR AND CALCULATION METHOD [patent_app_type] => utility [patent_app_number] => 17/751880 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751880 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751880
CALCULATOR AND CALCULATION METHOD May 23, 2022 Abandoned
Array ( [id] => 19375828 [patent_doc_number] => 12067398 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-08-20 [patent_title] => Shared learning table for load value prediction and load address prediction [patent_app_type] => utility [patent_app_number] => 17/661491 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17661491 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/661491
Shared learning table for load value prediction and load address prediction Apr 28, 2022 Issued
Array ( [id] => 18741697 [patent_doc_number] => 20230350678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => Instruction Set Architecture for Neural Network Quantization and Packing [patent_app_type] => utility [patent_app_number] => 17/732361 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732361 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/732361
Instruction set architecture for neural network quantization and packing Apr 27, 2022 Issued
Array ( [id] => 17778607 [patent_doc_number] => 20220244957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => Cache Preload Operations Using Streaming Engine [patent_app_type] => utility [patent_app_number] => 17/720657 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17720657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/720657
Cache preload operations using streaming engine Apr 13, 2022 Issued
Array ( [id] => 17751457 [patent_doc_number] => 20220229662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => SUPER-THREAD PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/716981 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17716981 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/716981
SUPER-THREAD PROCESSOR Apr 7, 2022 Abandoned
Array ( [id] => 19198203 [patent_doc_number] => 11995442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Processor having a register file, processing unit, and instruction sequencer, and operable with an instruction set having variable length instructions and a table that maps opcodes to register file addresses [patent_app_type] => utility [patent_app_number] => 17/658356 [patent_app_country] => US [patent_app_date] => 2022-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6228 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17658356 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/658356
Processor having a register file, processing unit, and instruction sequencer, and operable with an instruction set having variable length instructions and a table that maps opcodes to register file addresses Apr 6, 2022 Issued
Array ( [id] => 18677827 [patent_doc_number] => 20230315474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => MICROPROCESSOR WITH APPARATUS AND METHOD FOR REPLAYING INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/713569 [patent_app_country] => US [patent_app_date] => 2022-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17713569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/713569
Microprocessor with time count based instruction execution and replay Apr 4, 2022 Issued
Array ( [id] => 18677828 [patent_doc_number] => 20230315475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => MANAGING LARGE TAGE HISTORIES [patent_app_type] => utility [patent_app_number] => 17/708247 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708247 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/708247
MANAGING LARGE TAGE HISTORIES Mar 29, 2022 Abandoned
Array ( [id] => 18677807 [patent_doc_number] => 20230315454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => FUSING NO-OP (NOP) INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/708216 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708216 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/708216
FUSING NO-OP (NOP) INSTRUCTIONS Mar 29, 2022 Abandoned
Array ( [id] => 18677823 [patent_doc_number] => 20230315470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => CONTROL REGISTER SET TO FACILITATE PROCESSOR EVENT BASED SAMPLING [patent_app_type] => utility [patent_app_number] => 17/708933 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708933 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/708933
CONTROL REGISTER SET TO FACILITATE PROCESSOR EVENT BASED SAMPLING Mar 29, 2022 Pending
Array ( [id] => 18659843 [patent_doc_number] => 20230305850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => BRANCH PREDICTION USING SPECULATIVE INDEXING AND INTRALINE COUNT [patent_app_type] => utility [patent_app_number] => 17/703063 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703063 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/703063
Branch prediction using speculative indexing and intraline count Mar 23, 2022 Issued
Array ( [id] => 18703232 [patent_doc_number] => 11789742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Pipeline protection for CPUs with save and restore of intermediate results [patent_app_type] => utility [patent_app_number] => 17/688260 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9113 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17688260 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/688260
Pipeline protection for CPUs with save and restore of intermediate results Mar 6, 2022 Issued
Array ( [id] => 17690344 [patent_doc_number] => 20220197637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => EXPOSING VALID BYTE LANES AS VECTOR PREDICATES TO CPU [patent_app_type] => utility [patent_app_number] => 17/687780 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17687780 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/687780
Exposing valid byte lanes as vector predicates to CPU Mar 6, 2022 Issued
Array ( [id] => 18606642 [patent_doc_number] => 11748106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values [patent_app_type] => utility [patent_app_number] => 17/683564 [patent_app_country] => US [patent_app_date] => 2022-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 43 [patent_no_of_words] => 33454 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683564 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/683564
Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values Feb 28, 2022 Issued
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