Search

Matthew P. Coughlin

Examiner (ID: 19098, Phone: (571)270-1311 , Office: P/1626 )

Most Active Art Unit
1626
Art Unit(s)
1626
Total Applications
1390
Issued Applications
919
Pending Applications
92
Abandoned Applications
408

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19283795 [patent_doc_number] => 20240220271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => METHOD AND SYSTEM FOR ACCELERATING RECURRENT NEURAL NETWORK BASED ON CORTEX-M PROCESSOR, AND MEDIUM [patent_app_type] => utility [patent_app_number] => 17/918572 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17918572 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/918572
METHOD AND SYSTEM FOR ACCELERATING RECURRENT NEURAL NETWORK BASED ON CORTEX-M PROCESSOR, AND MEDIUM Feb 24, 2022 Abandoned
Array ( [id] => 19228731 [patent_doc_number] => 12008369 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-06-11 [patent_title] => Load instruction fusion [patent_app_type] => utility [patent_app_number] => 17/652501 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17652501 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/652501
Load instruction fusion Feb 24, 2022 Issued
Array ( [id] => 20481721 [patent_doc_number] => 12530196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Inserting null vectors into a stream of vectors [patent_app_type] => utility [patent_app_number] => 17/676910 [patent_app_country] => US [patent_app_date] => 2022-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 49 [patent_no_of_words] => 32504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676910 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/676910
Inserting null vectors into a stream of vectors Feb 21, 2022 Issued
Array ( [id] => 17643886 [patent_doc_number] => 20220171624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => APPARATUS AND METHOD FOR COMPLEX BY COMPLEX CONJUGATE MULTIPLICATION [patent_app_type] => utility [patent_app_number] => 17/672504 [patent_app_country] => US [patent_app_date] => 2022-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672504 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/672504
Apparatus and method for complex by complex conjugate multiplication Feb 14, 2022 Issued
Array ( [id] => 17722165 [patent_doc_number] => 20220214887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => Coprocessor Synchronizing Instruction Suppression [patent_app_type] => utility [patent_app_number] => 17/668869 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13651 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668869 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/668869
Coprocessor synchronizing instruction suppression Feb 9, 2022 Issued
Array ( [id] => 17884812 [patent_doc_number] => 20220300289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => OPERATION PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/666829 [patent_app_country] => US [patent_app_date] => 2022-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17666829 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/666829
OPERATION PROCESSING APPARATUS Feb 7, 2022 Pending
Array ( [id] => 18750560 [patent_doc_number] => 11809874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Conditional instructions distribution and execution on pipelines having different latencies for mispredictions [patent_app_type] => utility [patent_app_number] => 17/590722 [patent_app_country] => US [patent_app_date] => 2022-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 18036 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17590722 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/590722
Conditional instructions distribution and execution on pipelines having different latencies for mispredictions Jan 31, 2022 Issued
Array ( [id] => 19506935 [patent_doc_number] => 12118358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => One-dimensional zero padding in a stream of matrix elements [patent_app_type] => utility [patent_app_number] => 17/583380 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 49 [patent_no_of_words] => 36753 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17583380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/583380
One-dimensional zero padding in a stream of matrix elements Jan 24, 2022 Issued
Array ( [id] => 18471251 [patent_doc_number] => 20230205537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => METHODS AND APPARATUS FOR DECODING PROGRAM INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/560643 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4398 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560643 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/560643
Speculative usage of parallel decode units Dec 22, 2021 Issued
Array ( [id] => 17535365 [patent_doc_number] => 20220113974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => HARDWARE-SOFTWARE CO-DESIGNED MULTI-CAST FOR IN-MEMORY COMPUTING ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 17/561029 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561029 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561029
Hardware-software co-designed multi-cast for in-memory computing architectures Dec 22, 2021 Issued
Array ( [id] => 18271656 [patent_doc_number] => 20230092898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => Coprocessor Prefetcher [patent_app_type] => utility [patent_app_number] => 17/643765 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643765 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643765
Coprocessor prefetcher Dec 9, 2021 Issued
Array ( [id] => 17613788 [patent_doc_number] => 20220156068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => METHOD AND APPARATUS FOR MINIMALLY INTRUSIVE INSTRUCTION POINTER-AWARE PROCESSING RESOURCE ACTIVITY PROFILING [patent_app_type] => utility [patent_app_number] => 17/530040 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530040 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530040
METHOD AND APPARATUS FOR MINIMALLY INTRUSIVE INSTRUCTION POINTER-AWARE PROCESSING RESOURCE ACTIVITY PROFILING Nov 17, 2021 Pending
Array ( [id] => 19596081 [patent_doc_number] => 12153929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Processor that executes instruction that specifies instruction concatenation and atomicity [patent_app_type] => utility [patent_app_number] => 17/528403 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 5160 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17528403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/528403
Processor that executes instruction that specifies instruction concatenation and atomicity Nov 16, 2021 Issued
Array ( [id] => 17581116 [patent_doc_number] => 20220137971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => INSTRUCTION LENGTH BASED PARALLEL INSTRUCTION DEMARCATOR [patent_app_type] => utility [patent_app_number] => 17/526882 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14349 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/526882
Parallel instruction demarcator Nov 14, 2021 Issued
Array ( [id] => 18788051 [patent_doc_number] => 20230376449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SIGNAL PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 18/248180 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18248180 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/248180
SIGNAL PROCESSING DEVICE Nov 9, 2021 Pending
Array ( [id] => 17565124 [patent_doc_number] => 20220129273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => APPARATUS AND METHOD FOR VECTOR MULTIPLY AND SUBTRACTION OF SIGNED DOUBLEWORDS [patent_app_type] => utility [patent_app_number] => 17/518235 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518235 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518235
APPARATUS AND METHOD FOR VECTOR MULTIPLY AND SUBTRACTION OF SIGNED DOUBLEWORDS Nov 2, 2021 Abandoned
Array ( [id] => 17565118 [patent_doc_number] => 20220129267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => APPARATUS AND METHOD FOR RIGHT SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED DOUBLEWORDS [patent_app_type] => utility [patent_app_number] => 17/518291 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518291 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518291
APPARATUS AND METHOD FOR RIGHT SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED DOUBLEWORDS Nov 2, 2021 Pending
Array ( [id] => 17565119 [patent_doc_number] => 20220129268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => APPARATUS AND METHOD FOR RIGHT-SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED WORDS [patent_app_type] => utility [patent_app_number] => 17/518336 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518336 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518336
APPARATUS AND METHOD FOR RIGHT-SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED WORDS Nov 2, 2021 Abandoned
Array ( [id] => 18322468 [patent_doc_number] => 20230120596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => RESPONDING TO BRANCH MISPREDICTION FOR PREDICATED-LOOP-TERMINATING BRANCH INSTRUCTION [patent_app_type] => utility [patent_app_number] => 17/505854 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17505854 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/505854
Responding to branch misprediction for predicated-loop-terminating branch instruction Oct 19, 2021 Issued
Array ( [id] => 17372102 [patent_doc_number] => 20220027154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS [patent_app_type] => utility [patent_app_number] => 17/496632 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7007 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496632 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/496632
ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS Oct 6, 2021 Abandoned
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