Search

Matthew P. Coughlin

Examiner (ID: 19098, Phone: (571)270-1311 , Office: P/1626 )

Most Active Art Unit
1626
Art Unit(s)
1626
Total Applications
1390
Issued Applications
919
Pending Applications
92
Abandoned Applications
408

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17230659 [patent_doc_number] => 20210357216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => ENABLING REMOVAL AND RECONSTRUCTION OF FLAG OPERATIONS IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/335284 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335284 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/335284
Enabling removal and reconstruction of flag operations in a processor May 31, 2021 Issued
Array ( [id] => 18136116 [patent_doc_number] => 11561794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry [patent_app_type] => utility [patent_app_number] => 17/331085 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 14617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331085
Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry May 25, 2021 Issued
Array ( [id] => 17245523 [patent_doc_number] => 20210365267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => METHOD AND APPARATUS FOR INSTRUCTION EXPANSION FOR EMBEDDED DEVICE [patent_app_type] => utility [patent_app_number] => 17/326132 [patent_app_country] => US [patent_app_date] => 2021-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326132 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326132
METHOD AND APPARATUS FOR INSTRUCTION EXPANSION FOR EMBEDDED DEVICE May 19, 2021 Abandoned
Array ( [id] => 17977331 [patent_doc_number] => 11494191 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-08 [patent_title] => Tracking exact convergence to guide the recovery process in response to a mispredicted branch [patent_app_type] => utility [patent_app_number] => 17/323069 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9918 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323069 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/323069
Tracking exact convergence to guide the recovery process in response to a mispredicted branch May 17, 2021 Issued
Array ( [id] => 18234803 [patent_doc_number] => 11599361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Flushing a fetch queue using predecode circuitry and prediction information [patent_app_type] => utility [patent_app_number] => 17/315737 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8085 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315737
Flushing a fetch queue using predecode circuitry and prediction information May 9, 2021 Issued
Array ( [id] => 17202573 [patent_doc_number] => 20210342668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => Methods And Systems For Efficient Processing Of Recurrent Neural Networks [patent_app_type] => utility [patent_app_number] => 17/244797 [patent_app_country] => US [patent_app_date] => 2021-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17244797 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/244797
Methods And Systems For Efficient Processing Of Recurrent Neural Networks Apr 28, 2021 Pending
Array ( [id] => 19114803 [patent_doc_number] => 20240126553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => DATA PROCESSING METHOD AND APPARATUS, AND RELATED PRODUCT [patent_app_type] => utility [patent_app_number] => 17/619781 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17619781 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/619781
DATA PROCESSING METHOD AND APPARATUS, AND RELATED PRODUCT Apr 27, 2021 Pending
Array ( [id] => 17977330 [patent_doc_number] => 11494190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Circuitry and method for controlling a generated association of a physical register with a predicated processing operation based on predicate data state [patent_app_type] => utility [patent_app_number] => 17/218371 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5928 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/218371
Circuitry and method for controlling a generated association of a physical register with a predicated processing operation based on predicate data state Mar 30, 2021 Issued
Array ( [id] => 17915616 [patent_doc_number] => 20220318012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => PROCESSING-IN-MEMORY CONCURRENT PROCESSING SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/217792 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17217792 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/217792
Processing-in-memory concurrent processing system and method Mar 29, 2021 Issued
Array ( [id] => 17899226 [patent_doc_number] => 20220308888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => METHOD FOR REDUCING LOST CYCLES AFTER BRANCH MISPREDICTION IN A MULTI-THREAD MICROPROCESSOR [patent_app_type] => utility [patent_app_number] => 17/214805 [patent_app_country] => US [patent_app_date] => 2021-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214805 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214805
METHOD FOR REDUCING LOST CYCLES AFTER BRANCH MISPREDICTION IN A MULTI-THREAD MICROPROCESSOR Mar 26, 2021 Abandoned
Array ( [id] => 17899225 [patent_doc_number] => 20220308887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => MITIGATION OF BRANCH MISPREDICTION PENALTY IN A HARDWARE MULTI-THREAD MICROPROCESSOR [patent_app_type] => utility [patent_app_number] => 17/214802 [patent_app_country] => US [patent_app_date] => 2021-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214802
MITIGATION OF BRANCH MISPREDICTION PENALTY IN A HARDWARE MULTI-THREAD MICROPROCESSOR Mar 26, 2021 Abandoned
Array ( [id] => 18015086 [patent_doc_number] => 11507382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Systems and methods for virtually partitioning a machine perception and dense algorithm integrated circuit [patent_app_type] => utility [patent_app_number] => 17/214276 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10919 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214276 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214276
Systems and methods for virtually partitioning a machine perception and dense algorithm integrated circuit Mar 25, 2021 Issued
Array ( [id] => 17899219 [patent_doc_number] => 20220308881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => INSTRUCTION AND LOGIC FOR SUM OF ABSOLUTE DIFFERENCES [patent_app_type] => utility [patent_app_number] => 17/214291 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214291 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214291
INSTRUCTION AND LOGIC FOR SUM OF ABSOLUTE DIFFERENCES Mar 25, 2021 Abandoned
Array ( [id] => 17970012 [patent_doc_number] => 11487545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methods [patent_app_type] => utility [patent_app_number] => 17/192583 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7583 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192583 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/192583
Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methods Mar 3, 2021 Issued
Array ( [id] => 17853769 [patent_doc_number] => 20220283811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => LOOP BUFFERING EMPLOYING LOOP CHARACTERISTIC PREDICTION IN A PROCESSOR FOR OPTIMIZING LOOP BUFFER PERFORMANCE [patent_app_type] => utility [patent_app_number] => 17/191252 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17191252 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/191252
LOOP BUFFERING EMPLOYING LOOP CHARACTERISTIC PREDICTION IN A PROCESSOR FOR OPTIMIZING LOOP BUFFER PERFORMANCE Mar 2, 2021 Abandoned
Array ( [id] => 17667073 [patent_doc_number] => 11360769 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-14 [patent_title] => Decimal scale and convert and split to hexadecimal floating point instruction [patent_app_type] => utility [patent_app_number] => 17/186302 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 12305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17186302 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/186302
Decimal scale and convert and split to hexadecimal floating point instruction Feb 25, 2021 Issued
Array ( [id] => 17771164 [patent_doc_number] => 11403105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Detecting misprediction when an additional branch direction prediction determined using value prediction is considered more accurate than an initial branch direction prediction [patent_app_type] => utility [patent_app_number] => 17/158276 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10671 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158276 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158276
Detecting misprediction when an additional branch direction prediction determined using value prediction is considered more accurate than an initial branch direction prediction Jan 25, 2021 Issued
Array ( [id] => 17924588 [patent_doc_number] => 11467836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Executing cross-core copy instructions in an accelerator to temporarily store an operand that cannot be accommodated by on-chip memory of a primary core into a secondary core [patent_app_type] => utility [patent_app_number] => 17/158685 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 18828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158685 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158685
Executing cross-core copy instructions in an accelerator to temporarily store an operand that cannot be accommodated by on-chip memory of a primary core into a secondary core Jan 25, 2021 Issued
Array ( [id] => 19427170 [patent_doc_number] => 12086593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Capability-generating address calculating instruction [patent_app_type] => utility [patent_app_number] => 17/904167 [patent_app_country] => US [patent_app_date] => 2021-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 20933 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17904167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/904167
Capability-generating address calculating instruction Jan 6, 2021 Issued
Array ( [id] => 19552759 [patent_doc_number] => 12136470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Processing-in-memory (PIM) system that changes between multiplication/accumulation (MAC) and memory modes and operating methods of the PIM system [patent_app_type] => utility [patent_app_number] => 17/143941 [patent_app_country] => US [patent_app_date] => 2021-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 56 [patent_no_of_words] => 42903 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17143941 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/143941
Processing-in-memory (PIM) system that changes between multiplication/accumulation (MAC) and memory modes and operating methods of the PIM system Jan 6, 2021 Issued
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