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Matthew P. Coughlin

Examiner (ID: 19098, Phone: (571)270-1311 , Office: P/1626 )

Most Active Art Unit
1626
Art Unit(s)
1626
Total Applications
1390
Issued Applications
919
Pending Applications
92
Abandoned Applications
408

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17690350 [patent_doc_number] => 20220197643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => SPECULATIVE DECOMPRESSION WITHIN PROCESSOR CORE CACHES [patent_app_type] => utility [patent_app_number] => 17/133618 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133618 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133618
SPECULATIVE DECOMPRESSION WITHIN PROCESSOR CORE CACHES Dec 22, 2020 Abandoned
Array ( [id] => 17690361 [patent_doc_number] => 20220197654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => APPARATUS AND METHOD FOR COMPLEX MATRIX CONJUGATE TRANSPOSE [patent_app_type] => utility [patent_app_number] => 17/133400 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133400 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133400
APPARATUS AND METHOD FOR COMPLEX MATRIX CONJUGATE TRANSPOSE Dec 22, 2020 Abandoned
Array ( [id] => 17565614 [patent_doc_number] => 20220129763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => HIGH CONFIDENCE MULTIPLE BRANCH OFFSET PREDICTOR [patent_app_type] => utility [patent_app_number] => 17/130661 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130661 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/130661
HIGH CONFIDENCE MULTIPLE BRANCH OFFSET PREDICTOR Dec 21, 2020 Abandoned
Array ( [id] => 17846645 [patent_doc_number] => 11436018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Apparatuses, methods, and systems for instructions to request a history reset of a processor core [patent_app_type] => utility [patent_app_number] => 17/124813 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 28471 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124813 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124813
Apparatuses, methods, and systems for instructions to request a history reset of a processor core Dec 16, 2020 Issued
Array ( [id] => 17589484 [patent_doc_number] => 11327757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Processor providing intelligent management of values buffered in overlaid architected and non-architected register files [patent_app_type] => utility [patent_app_number] => 17/120979 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120979 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120979
Processor providing intelligent management of values buffered in overlaid architected and non-architected register files Dec 13, 2020 Issued
Array ( [id] => 16856850 [patent_doc_number] => 20210157595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => AUTOMATED CONCURRENCY AND REPETITION WITH MINIMAL SYNTAX [patent_app_type] => utility [patent_app_number] => 17/105695 [patent_app_country] => US [patent_app_date] => 2020-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17105695 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/105695
Automated concurrency and repetition with minimal syntax Nov 26, 2020 Issued
Array ( [id] => 17744465 [patent_doc_number] => 11392535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Loading operands and outputting results from a multi-dimensional array using only a single side [patent_app_type] => utility [patent_app_number] => 17/104465 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 13832 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104465 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104465
Loading operands and outputting results from a multi-dimensional array using only a single side Nov 24, 2020 Issued
Array ( [id] => 20203020 [patent_doc_number] => 12405799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Register rename stage fusing of instructions [patent_app_type] => utility [patent_app_number] => 16/952661 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 3366 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 417 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16952661 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/952661
Register rename stage fusing of instructions Nov 18, 2020 Issued
Array ( [id] => 17999536 [patent_doc_number] => 11500643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Spectre fixes with indirect valid table [patent_app_type] => utility [patent_app_number] => 17/098195 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8092 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098195 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/098195
Spectre fixes with indirect valid table Nov 12, 2020 Issued
Array ( [id] => 18276000 [patent_doc_number] => 11614944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Small branch predictor escape [patent_app_type] => utility [patent_app_number] => 17/092668 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7887 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17092668 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/092668
Small branch predictor escape Nov 8, 2020 Issued
Array ( [id] => 17622030 [patent_doc_number] => 11341086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Compute accelerator with 3D data flows [patent_app_type] => utility [patent_app_number] => 17/093227 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7368 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093227 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/093227
Compute accelerator with 3D data flows Nov 8, 2020 Issued
Array ( [id] => 18125248 [patent_doc_number] => 20230010863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => INTERMODAL CALLING BRANCH INSTRUCTION [patent_app_type] => utility [patent_app_number] => 17/757197 [patent_app_country] => US [patent_app_date] => 2020-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17757197 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/757197
Intermodal calling branch instruction Nov 4, 2020 Issued
Array ( [id] => 17744320 [patent_doc_number] => 11392387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processor [patent_app_type] => utility [patent_app_number] => 17/089379 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 15790 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089379 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/089379
Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processor Nov 3, 2020 Issued
Array ( [id] => 16794772 [patent_doc_number] => 20210124589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => EVENT HANDLING IN PIPELINE EXECUTE STAGES [patent_app_type] => utility [patent_app_number] => 17/079105 [patent_app_country] => US [patent_app_date] => 2020-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17079105 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/079105
Storing a result of a first instruction of an execute packet in a holding register prior to completion of a second instruction of the execute packet Oct 22, 2020 Issued
Array ( [id] => 17408884 [patent_doc_number] => 11249766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-15 [patent_title] => Coprocessor synchronizing instruction suppression [patent_app_type] => utility [patent_app_number] => 17/077654 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077654 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/077654
Coprocessor synchronizing instruction suppression Oct 21, 2020 Issued
Array ( [id] => 17550101 [patent_doc_number] => 20220121443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => THREAD-BASED PROCESSOR HALTING [patent_app_type] => utility [patent_app_number] => 17/074730 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074730 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/074730
Thread-based processor halting Oct 19, 2020 Issued
Array ( [id] => 16751434 [patent_doc_number] => 20210103443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => ENHANCED SECURITY COMPUTER PROCESSOR WITH MENTOR CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/074491 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074491 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/074491
ENHANCED SECURITY COMPUTER PROCESSOR WITH MENTOR CIRCUITS Oct 18, 2020 Abandoned
Array ( [id] => 16659297 [patent_doc_number] => 20210055934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => ARRAY-BASED INFERENCE ENGINE FOR MACHINE LEARNING [patent_app_type] => utility [patent_app_number] => 16/948867 [patent_app_country] => US [patent_app_date] => 2020-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16948867 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/948867
ARRAY-BASED INFERENCE ENGINE FOR MACHINE LEARNING Oct 1, 2020 Abandoned
Array ( [id] => 17507414 [patent_doc_number] => 20220100517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => SM4 NEW INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/033741 [patent_app_country] => US [patent_app_date] => 2020-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033741 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033741
SM4 NEW INSTRUCTIONS Sep 25, 2020 Abandoned
Array ( [id] => 18430376 [patent_doc_number] => 11675595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Starting reading of instructions from a correct speculative condition prior to fully flushing an instruction pipeline after an incorrect instruction speculation determination [patent_app_type] => utility [patent_app_number] => 17/031397 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11343 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 473 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031397 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031397
Starting reading of instructions from a correct speculative condition prior to fully flushing an instruction pipeline after an incorrect instruction speculation determination Sep 23, 2020 Issued
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