Search

Matthew Van Nguyen

Examiner (ID: 2065, Phone: (571)272-2081 , Office: P/2838 )

Most Active Art Unit
2838
Art Unit(s)
2839, 2102, 2111, 2838
Total Applications
3253
Issued Applications
3031
Pending Applications
87
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19660912 [patent_doc_number] => 20240427977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => QUICK SIMULATION AND OPTIMIZATION METHOD AND SYSTEM FOR ANALOG CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/823587 [patent_app_country] => US [patent_app_date] => 2024-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 504 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18823587 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/823587
Quick simulation and optimization method and system for analog circuits Sep 2, 2024 Issued
Array ( [id] => 20773006 [patent_doc_number] => 12656675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Mask optimization accounting for more critical and less critical overlap regions [patent_app_type] => utility [patent_app_number] => 18/814432 [patent_app_country] => US [patent_app_date] => 2024-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 43 [patent_no_of_words] => 33060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18814432 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/814432
Mask optimization accounting for more critical and less critical overlap regions Aug 22, 2024 Issued
Array ( [id] => 20790427 [patent_doc_number] => 12664343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => System and method for performing scan chain ECO [patent_app_type] => utility [patent_app_number] => 18/808431 [patent_app_country] => US [patent_app_date] => 2024-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 424 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18808431 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/808431
SYSTEM AND METHOD FOR PERFORMING SCAN CHAIN ECO Aug 18, 2024 Issued
Array ( [id] => 20494484 [patent_doc_number] => 12536356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Circuit design visibility in integrated circuit devices [patent_app_type] => utility [patent_app_number] => 18/665300 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1154 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665300 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/665300
Circuit design visibility in integrated circuit devices May 14, 2024 Issued
Array ( [id] => 19332007 [patent_doc_number] => 20240246437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => SYSTEMS AND MOBILE APPLICATION FOR ELECTRIC WIRELESS CHARGING STATIONS [patent_app_type] => utility [patent_app_number] => 18/625700 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625700
SYSTEMS AND MOBILE APPLICATION FOR ELECTRIC WIRELESS CHARGING STATIONS Apr 2, 2024 Pending
Array ( [id] => 19857322 [patent_doc_number] => 12260160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Fabricated layout correlation [patent_app_type] => utility [patent_app_number] => 18/408018 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408018 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408018
Fabricated layout correlation Jan 8, 2024 Issued
Array ( [id] => 19174848 [patent_doc_number] => 20240160822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SYSTEM AND METHOD FOR USING INTERFACE PROTECTION PARAMETERS [patent_app_type] => utility [patent_app_number] => 18/539238 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/539238
System and method for using interface protection parameters Dec 12, 2023 Issued
Array ( [id] => 19036773 [patent_doc_number] => 20240086588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => Systems and Methods for Managing Energy Storage Devices [patent_app_type] => utility [patent_app_number] => 18/504028 [patent_app_country] => US [patent_app_date] => 2023-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 71337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18504028 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/504028
Systems and Methods for Managing Energy Storage Devices Nov 6, 2023 Pending
Array ( [id] => 19008502 [patent_doc_number] => 20240072573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => Wireless Power System With Voltage Regulation [patent_app_type] => utility [patent_app_number] => 18/503389 [patent_app_country] => US [patent_app_date] => 2023-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18503389 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/503389
Wireless power system with voltage regulation Nov 6, 2023 Issued
Array ( [id] => 19719450 [patent_doc_number] => 12204990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Error corrected variational algorithms [patent_app_type] => utility [patent_app_number] => 18/499879 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499879 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499879
Error corrected variational algorithms Oct 31, 2023 Issued
Array ( [id] => 18897490 [patent_doc_number] => 20240012975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => LOGIC CELL STRUCTURES AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/472280 [patent_app_country] => US [patent_app_date] => 2023-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18472280 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/472280
Logic cell structures and related methods Sep 21, 2023 Issued
Array ( [id] => 19304018 [patent_doc_number] => 20240232598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => GENERAL PADDING SUPPORT FOR CONVOLUTION ON SYSTOLIC ARRAYS [patent_app_type] => utility [patent_app_number] => 18/469272 [patent_app_country] => US [patent_app_date] => 2023-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469272 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/469272
General padding support for convolution on systolic arrays Sep 17, 2023 Issued
Array ( [id] => 19406017 [patent_doc_number] => 20240289528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => METHOD AND SYSTEM FOR AUTOMATICALLY CHECKING CIRCUIT LAYOUT OF PRINTED CIRCUIT BOARD [patent_app_type] => utility [patent_app_number] => 18/449407 [patent_app_country] => US [patent_app_date] => 2023-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18449407 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/449407
METHOD AND SYSTEM FOR AUTOMATICALLY CHECKING CIRCUIT LAYOUT OF PRINTED CIRCUIT BOARD Aug 13, 2023 Pending
Array ( [id] => 18832843 [patent_doc_number] => 20230401370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR INTEGRATED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 18/446739 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11520 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446739 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446739
METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR INTEGRATED CIRCUIT DESIGN Aug 8, 2023 Pending
Array ( [id] => 18896852 [patent_doc_number] => 20240012337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => METHOD OF DETERMINING CONTROL PARAMETERS OF A DEVICE MANUFACTURING PROCESS [patent_app_type] => utility [patent_app_number] => 18/229984 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18229984 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/229984
Method of determining control parameters of a device manufacturing process Aug 2, 2023 Issued
Array ( [id] => 19669736 [patent_doc_number] => 12182488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Semiconductor device including standard-cell-adapted power grid arrangement [patent_app_type] => utility [patent_app_number] => 18/362839 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 13469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362839 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362839
Semiconductor device including standard-cell-adapted power grid arrangement Jul 30, 2023 Issued
Array ( [id] => 18942174 [patent_doc_number] => 20240037313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => STATISTICAL GRAPH CIRCUIT COMPONENT PROBABILITY MODEL FOR AN INTEGRATED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 18/226188 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226188 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/226188
STATISTICAL GRAPH CIRCUIT COMPONENT PROBABILITY MODEL FOR AN INTEGRATED CIRCUIT DESIGN Jul 24, 2023 Pending
Array ( [id] => 19942512 [patent_doc_number] => 12314644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Integrated circuit design method, system and computer program product [patent_app_type] => utility [patent_app_number] => 18/356426 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 8545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356426 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356426
Integrated circuit design method, system and computer program product Jul 20, 2023 Issued
Array ( [id] => 19686701 [patent_doc_number] => 20250005246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => COMPILING A TENSOR TILING SPECIFICATION TO MULTI-DIMENSIONAL DATA MOVER CIRCUIT CONFIGURATIONS [patent_app_type] => utility [patent_app_number] => 18/345393 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11987 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345393 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345393
COMPILING A TENSOR TILING SPECIFICATION TO MULTI-DIMENSIONAL DATA MOVER CIRCUIT CONFIGURATIONS Jun 29, 2023 Pending
Array ( [id] => 19686707 [patent_doc_number] => 20250005252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => YIELDING AND ROUTABLE CIRCUIT CO-DESIGN USING VIABARS [patent_app_type] => utility [patent_app_number] => 18/344788 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344788 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344788
YIELDING AND ROUTABLE CIRCUIT CO-DESIGN USING VIABARS Jun 28, 2023 Pending
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