Matthew Van Nguyen

Array ( [id] => 20036320 [patent_doc_number] => 20250174542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => SEMICONDUCTOR ASSEMBLY COMPRISING A 3D BLOCK AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 19/030747 [patent_app_country] => US [patent_app_date] => 2025-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10017 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19030747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19951305 [patent_doc_number] => 12322676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-03 [patent_title] => Baffles for electronic circuits immersed in cooling fluid in a tank [patent_app_type] => utility [patent_app_number] => 18/967181 [patent_app_country] => US [patent_app_date] => 2024-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 6811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18967181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19790171 [patent_doc_number] => 20250063850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => PRODUCT, SYSTEM, AND METHOD WITH SILVER NANOSTRUCTURES THIN FILM FOR INFRARED PHOTODETECTOR [patent_app_type] => utility [patent_app_number] => 18/804273 [patent_app_country] => US [patent_app_date] => 2024-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18804273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19531796 [patent_doc_number] => 20240355698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => MANUFACTURING METHOD OF SENSING DIE ENCAPSULATED BY ENCAPSULANT WITH ROUGHNESS SURFACE HAVING HOLLOW REGION [patent_app_type] => utility [patent_app_number] => 18/762656 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20496929 [patent_doc_number] => 12538823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Power delivery for embedded bridge die utilizing trench structures [patent_app_type] => utility [patent_app_number] => 18/759008 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 1094 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20089098 [patent_doc_number] => 20250219034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/751021 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19496894 [patent_doc_number] => 20240335912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => METHOD OF FORMING A LAYER STRUCTURE, CHIP PACKAGE AND CHIP ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 18/750260 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18750260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20089031 [patent_doc_number] => 20250218967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/751105 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20274891 [patent_doc_number] => 12444676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Self-aligned via for interconnect structure [patent_app_type] => utility [patent_app_number] => 18/745773 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 1150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745773 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19484070 [patent_doc_number] => 20240332112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => CHIP-SCALE PACKAGE ARCHITECTURES CONTAINING A DIE BACK SIDE METAL AND A SOLDER THERMAL INTERFACE MATERIAL [patent_app_type] => utility [patent_app_number] => 18/744108 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19646532 [patent_doc_number] => 20240421052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => MULTI-CHIP OR MULTI-CHIPLET FAN-OUT DEVICE FOR LAMINATE AND LEADFRAME PACKAGES [patent_app_type] => utility [patent_app_number] => 18/742517 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19468126 [patent_doc_number] => 20240321796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => PACKAGE STRUCTURE INCLUDING STACKED PILLAR PORTIONS AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/735126 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20305436 [patent_doc_number] => 12451436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Interconnecting a plurality of dies having spare input/output circuit [patent_app_type] => utility [patent_app_number] => 18/671478 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 3376 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19394934 [patent_doc_number] => 20240284804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => METHOD OF MANUFACTURING A MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) [patent_app_type] => utility [patent_app_number] => 18/642280 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19654672 [patent_doc_number] => 12176473 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-24 [patent_title] => LED packaging structure [patent_app_type] => utility [patent_app_number] => 18/632494 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4193 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19384706 [patent_doc_number] => 20240274576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => DIRECT BONDING IN MICROELECTRONIC ASSEMBLIES [patent_app_type] => utility [patent_app_number] => 18/632919 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19654463 [patent_doc_number] => 12176263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Integrated cooling assembly including coolant channel on the backside semiconductor device [patent_app_type] => utility [patent_app_number] => 18/620753 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620753 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19926281 [patent_doc_number] => 12300574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Adhesive and thermal interface material on a plurality of dies covered by a lid [patent_app_type] => utility [patent_app_number] => 18/432061 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 2233 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20140920 [patent_doc_number] => 20250247964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => INTEGRATED CIRCUIT (IC) ASSEMBLY INCLUDING A DIRECT CONNECTION PAD STRUCTURE FOR A SURFACE-MOUNT DEVICE (SMD) [patent_app_type] => utility [patent_app_number] => 18/426969 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426969 [rel_patent_id] =>[rel_patent_doc_number] =>)