Search

Matthew Van Nguyen

Examiner (ID: 2067, Phone: (571)272-2081 , Office: P/2838 )

Most Active Art Unit
2838
Art Unit(s)
2839, 2111, 2838, 2102
Total Applications
3253
Issued Applications
3031
Pending Applications
87
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18848755 [patent_doc_number] => 20230411159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => LASER IRRADIATION APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 18/035775 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18035775 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/035775
LASER IRRADIATION APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS Nov 4, 2021 Pending
Array ( [id] => 18326491 [patent_doc_number] => 20230124619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => CAVITY FORMED IN A MOLDING COMPOUND OF A SEMICONDUCTOR PACKAGE TO REDUCE MECHANICAL STRESS ON A PORTION OF A DIE IN THE PACKAGE, AND METHODS OF FORMATION [patent_app_type] => utility [patent_app_number] => 17/453202 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4638 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453202 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453202
Cavity formed in a molding compound of a semiconductor package to reduce mechanical stress on a portion of a die in the package, and methods of formation Nov 1, 2021 Issued
Array ( [id] => 17417401 [patent_doc_number] => 20220052305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => ORGANIC LIGHT-EMITTING APPARATUS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/516494 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17516494 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/516494
Organic light-emitting apparatus Oct 31, 2021 Issued
Array ( [id] => 17417066 [patent_doc_number] => 20220051970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => INTERPOSER AND SEMICONDUCTOR PACKAGE HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 17/511879 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17511879 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/511879
Wiring protection layer on an interposer with a through electrode Oct 26, 2021 Issued
Array ( [id] => 18042255 [patent_doc_number] => 20220386472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => CIRCUIT BOARD PREPARATION METHOD [patent_app_type] => utility [patent_app_number] => 17/503360 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17503360 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/503360
Circuit board preparation method Oct 17, 2021 Issued
Array ( [id] => 18913041 [patent_doc_number] => 11876028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Package with electrically insulated carrier and at least one step on encapsulant [patent_app_type] => utility [patent_app_number] => 17/502082 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 35 [patent_no_of_words] => 12414 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502082 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/502082
Package with electrically insulated carrier and at least one step on encapsulant Oct 14, 2021 Issued
Array ( [id] => 18494220 [patent_doc_number] => 11699641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/499018 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 9324 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 420 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499018 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499018
Semiconductor device Oct 11, 2021 Issued
Array ( [id] => 19401240 [patent_doc_number] => 12075652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Light-emitting device, display device, imaging device, and electronic device, with substrate, lens including convex curved surface portion, and light-emitting part between surface of substrate and lens [patent_app_type] => utility [patent_app_number] => 17/495947 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 13175 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495947 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495947
Light-emitting device, display device, imaging device, and electronic device, with substrate, lens including convex curved surface portion, and light-emitting part between surface of substrate and lens Oct 6, 2021 Issued
Array ( [id] => 18520787 [patent_doc_number] => 11710681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Semiconductor packages and methods of packaging semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/495788 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6249 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495788 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495788
Semiconductor packages and methods of packaging semiconductor devices Oct 5, 2021 Issued
Array ( [id] => 18653150 [patent_doc_number] => 20230298990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/023272 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18023272 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/023272
SEMICONDUCTOR DEVICE Oct 5, 2021 Pending
Array ( [id] => 17536828 [patent_doc_number] => 20220115437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => WAFER HAVING AUXILIARY PATTERN FOR ALIGNING LIGHT EMITTING DEVICE AND METHOD OF FABRICATING UNIT PIXEL USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/495451 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495451 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495451
Wafer having auxiliary pattern for aligning light emitting device and method of fabricating unit pixel using the same Oct 5, 2021 Issued
Array ( [id] => 19314437 [patent_doc_number] => 12040263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Semiconductor device with die mounted to an insulating substrate and corresponding method of manufacturing semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/487772 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5585 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487772 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/487772
Semiconductor device with die mounted to an insulating substrate and corresponding method of manufacturing semiconductor devices Sep 27, 2021 Issued
Array ( [id] => 18269207 [patent_doc_number] => 20230090449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO PRODUCE INTEGRATED CIRCUIT PACKAGES WITH NANO-ROUGHENED INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 17/448693 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6404 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448693 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448693
METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO PRODUCE INTEGRATED CIRCUIT PACKAGES WITH NANO-ROUGHENED INTERCONNECTS Sep 22, 2021 Pending
Array ( [id] => 17347148 [patent_doc_number] => 20220013479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => METHOD FOR FORMING CONDUCTIVE LAYER, AND CONDUCTIVE STRUCTURE AND FORMING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 17/448664 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448664 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448664
Method for forming conductive layer, and conductive structure and forming method therefor Sep 22, 2021 Issued
Array ( [id] => 18266125 [patent_doc_number] => 20230087367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => MICROELECTRONIC ASSEMBLIES WITH THROUGH DIE ATTACH FILM CONNECTIONS [patent_app_type] => utility [patent_app_number] => 17/481506 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481506 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/481506
MICROELECTRONIC ASSEMBLIES WITH THROUGH DIE ATTACH FILM CONNECTIONS Sep 21, 2021 Pending
Array ( [id] => 17463723 [patent_doc_number] => 20220077029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/468595 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468595 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468595
Porous body on the side surface of a connector mounted to semiconductor device Sep 6, 2021 Issued
Array ( [id] => 18767017 [patent_doc_number] => 11817429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Plurality of chips between two heat sinks [patent_app_type] => utility [patent_app_number] => 17/464914 [patent_app_country] => US [patent_app_date] => 2021-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 41 [patent_no_of_words] => 22393 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464914 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464914
Plurality of chips between two heat sinks Sep 1, 2021 Issued
Array ( [id] => 18224268 [patent_doc_number] => 20230063262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => DIE PAD RECESSES [patent_app_type] => utility [patent_app_number] => 17/463124 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463124 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463124
Semiconductor die mounted in a recess of die pad Aug 30, 2021 Issued
Array ( [id] => 18447069 [patent_doc_number] => 11682645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Plurality of stacked pillar portions on a semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/458551 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6707 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458551 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458551
Plurality of stacked pillar portions on a semiconductor structure Aug 26, 2021 Issued
Array ( [id] => 19168479 [patent_doc_number] => 11984392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Semiconductor package having a chip carrier with a pad offset feature [patent_app_type] => utility [patent_app_number] => 17/459296 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 12867 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459296 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459296
Semiconductor package having a chip carrier with a pad offset feature Aug 26, 2021 Issued
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