Search

Matthew Van Nguyen

Examiner (ID: 2067, Phone: (571)272-2081 , Office: P/2838 )

Most Active Art Unit
2838
Art Unit(s)
2839, 2111, 2838, 2102
Total Applications
3253
Issued Applications
3031
Pending Applications
87
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17918066 [patent_doc_number] => 20220320462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => DISPLAY PANEL, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/568446 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6880 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568446 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568446
Method for treating transparent adhesive layer of protective film on display back plate of display panel Jan 3, 2022 Issued
Array ( [id] => 17536979 [patent_doc_number] => 20220115588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => METHOD OF MANUFACTURING A MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) [patent_app_type] => utility [patent_app_number] => 17/560922 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560922 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/560922
Method of manufacturing a magnetoresistive random access memory (MRAM) Dec 22, 2021 Issued
Array ( [id] => 17536920 [patent_doc_number] => 20220115529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/559148 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559148 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559148
Semiconductor device and method for manufacturing the same Dec 21, 2021 Issued
Array ( [id] => 17933259 [patent_doc_number] => 20220328385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/557196 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557196 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/557196
Plurality of transistors attached to a heat sink with a periphery notch Dec 20, 2021 Issued
Array ( [id] => 19183792 [patent_doc_number] => 11990393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Semiconductor device including resin with a filler for encapsulating bridge member connected to a substrate [patent_app_type] => utility [patent_app_number] => 17/557165 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5012 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557165 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/557165
Semiconductor device including resin with a filler for encapsulating bridge member connected to a substrate Dec 20, 2021 Issued
Array ( [id] => 19888382 [patent_doc_number] => 12274132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Method of fabricating overflow drainage region in pixel definition bar for OLED display device [patent_app_type] => utility [patent_app_number] => 17/622845 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4076 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17622845 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/622845
Method of fabricating overflow drainage region in pixel definition bar for OLED display device Dec 20, 2021 Issued
Array ( [id] => 17692456 [patent_doc_number] => 20220199749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/555615 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14047 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555615 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555615
Coating layer disposed on a plurality of conductive particles between a display panel and a printed circuit board Dec 19, 2021 Issued
Array ( [id] => 19796454 [patent_doc_number] => 12237426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Floating gate based 3-terminal analog synapse device [patent_app_type] => utility [patent_app_number] => 17/553109 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 10264 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553109 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/553109
Floating gate based 3-terminal analog synapse device Dec 15, 2021 Issued
Array ( [id] => 19294596 [patent_doc_number] => 12033960 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-09 [patent_title] => Semiconductor package with stiffener ring having elevated opening [patent_app_type] => utility [patent_app_number] => 17/548325 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4452 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548325
Semiconductor package with stiffener ring having elevated opening Dec 9, 2021 Issued
Array ( [id] => 19277338 [patent_doc_number] => 12027470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Package carrier having a stiffener between solder bumps [patent_app_type] => utility [patent_app_number] => 17/547200 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 33 [patent_no_of_words] => 5984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/547200
Package carrier having a stiffener between solder bumps Dec 8, 2021 Issued
Array ( [id] => 18440030 [patent_doc_number] => 20230187325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => RADIO FREQUENCY PACKAGES CONTAINING SUBSTRATES WITH COEFFICIENT OF THERMAL EXPANSION MATCHED MOUNT PADS AND ASSOCIATED FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 17/546453 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17522 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546453
Radio frequency packages containing substrates with coefficient of thermal expansion matched mount pads and associated fabrication methods Dec 8, 2021 Issued
Array ( [id] => 19046687 [patent_doc_number] => 11935807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Plurality of dies electrically connected to a printed circuit board by a clip [patent_app_type] => utility [patent_app_number] => 17/542645 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1594 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542645 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542645
Plurality of dies electrically connected to a printed circuit board by a clip Dec 5, 2021 Issued
Array ( [id] => 17486012 [patent_doc_number] => 20220093516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => POWER DELIVERY FOR EMBEDDED BRIDGE DIE UTILIZING TRENCH STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/540141 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6324 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17540141 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/540141
Power delivery for embedded bridge die utilizing trench structures Nov 30, 2021 Issued
Array ( [id] => 17645280 [patent_doc_number] => 20220173019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => LEAD FRAME, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF LEAD FRAME [patent_app_type] => utility [patent_app_number] => 17/536713 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536713 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/536713
Lead frame with a support portion having a through hole over a heat dissipation plate, semiconductor device, and manufacturing method of lead frame Nov 28, 2021 Issued
Array ( [id] => 19376633 [patent_doc_number] => 12068213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Chip package and semiconductor arrangement having thermally conductive material in contact with a semiconductor chip and methods of forming thereof [patent_app_type] => utility [patent_app_number] => 17/531867 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 36 [patent_no_of_words] => 5608 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531867 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531867
Chip package and semiconductor arrangement having thermally conductive material in contact with a semiconductor chip and methods of forming thereof Nov 21, 2021 Issued
Array ( [id] => 18068166 [patent_doc_number] => 20220399254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/531736 [patent_app_country] => US [patent_app_date] => 2021-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531736 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531736
Package structure having a plurality of chips attached to a lead frame by redistribution layer Nov 19, 2021 Issued
Array ( [id] => 18967487 [patent_doc_number] => 11901268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Package with an electrode-attached frame supported by a heat sink, and method for manufacturing power semiconductor module provided therewith [patent_app_type] => utility [patent_app_number] => 17/455709 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11621 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455709 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455709
Package with an electrode-attached frame supported by a heat sink, and method for manufacturing power semiconductor module provided therewith Nov 18, 2021 Issued
Array ( [id] => 18337630 [patent_doc_number] => 20230129579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => HIGH ELECTRON MOBILITY TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/528159 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17528159 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/528159
High electron mobility transistor device having a barrier layer with a protruding portion Nov 15, 2021 Issued
Array ( [id] => 19229707 [patent_doc_number] => 12009351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Plurality of semiconductor devices between stacked substrates [patent_app_type] => utility [patent_app_number] => 17/525833 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 55 [patent_no_of_words] => 18584 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17525833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/525833
Plurality of semiconductor devices between stacked substrates Nov 11, 2021 Issued
Array ( [id] => 18983582 [patent_doc_number] => 11908771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Power semiconductor device with dual heat dissipation structures [patent_app_type] => utility [patent_app_number] => 17/524879 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 6206 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524879 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/524879
Power semiconductor device with dual heat dissipation structures Nov 11, 2021 Issued
Menu