
Matthew W. Such
Supervisory Patent Examiner (ID: 19436, Phone: (571)272-8895 , Office: P/2896 )
| Most Active Art Unit | 2891 |
| Art Unit(s) | 2891, 2896 |
| Total Applications | 458 |
| Issued Applications | 259 |
| Pending Applications | 15 |
| Abandoned Applications | 184 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1470375
[patent_doc_number] => 06459745
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-01
[patent_title] => 'Frequency/timing recovery circuit for orthogonal frequency division multiplexed signals'
[patent_app_type] => B1
[patent_app_number] => 09/404003
[patent_app_country] => US
[patent_app_date] => 1999-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 3392
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/459/06459745.pdf
[firstpage_image] =>[orig_patent_app_number] => 09404003
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/404003 | Frequency/timing recovery circuit for orthogonal frequency division multiplexed signals | Sep 22, 1999 | Issued |
Array
(
[id] => 1355920
[patent_doc_number] => 06587520
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-01
[patent_title] => 'Generation of amplitude levels for a partial response maximum likelihood (PRML) bit detector'
[patent_app_type] => B1
[patent_app_number] => 09/399600
[patent_app_country] => US
[patent_app_date] => 1999-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 4559
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 321
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/587/06587520.pdf
[firstpage_image] =>[orig_patent_app_number] => 09399600
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/399600 | Generation of amplitude levels for a partial response maximum likelihood (PRML) bit detector | Sep 19, 1999 | Issued |
Array
(
[id] => 1307386
[patent_doc_number] => 06625222
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-23
[patent_title] => 'Apparatus and method for high-speed wireless upstream data transmission using CATV-compatible modems'
[patent_app_type] => B1
[patent_app_number] => 09/397402
[patent_app_country] => US
[patent_app_date] => 1999-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5765
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/625/06625222.pdf
[firstpage_image] =>[orig_patent_app_number] => 09397402
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/397402 | Apparatus and method for high-speed wireless upstream data transmission using CATV-compatible modems | Sep 15, 1999 | Issued |
Array
(
[id] => 1404525
[patent_doc_number] => 06553066
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-22
[patent_title] => 'Time error compensation arrangement and multi-carrier modem comprising the arrangement'
[patent_app_type] => B1
[patent_app_number] => 09/393303
[patent_app_country] => US
[patent_app_date] => 1999-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4399
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/553/06553066.pdf
[firstpage_image] =>[orig_patent_app_number] => 09393303
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/393303 | Time error compensation arrangement and multi-carrier modem comprising the arrangement | Sep 9, 1999 | Issued |
Array
(
[id] => 7615933
[patent_doc_number] => 06947512
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-09-20
[patent_title] => 'Carrier reproducing circuit'
[patent_app_type] => utility
[patent_app_number] => 09/763958
[patent_app_country] => US
[patent_app_date] => 1999-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4785
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/947/06947512.pdf
[firstpage_image] =>[orig_patent_app_number] => 09763958
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/763958 | Carrier reproducing circuit | Aug 25, 1999 | Issued |
| 09/374258 | SIGNAL PROCESSING METHOD AND APPARATUS FOR ENSURING A DESIRED RELATIONSHIP BETWEEN SIGNALS | Aug 12, 1999 | Abandoned |
Array
(
[id] => 1409303
[patent_doc_number] => 06549593
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-15
[patent_title] => 'Interface apparatus for interfacing data to a plurality of different clock domains'
[patent_app_type] => B1
[patent_app_number] => 09/356820
[patent_app_country] => US
[patent_app_date] => 1999-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 2994
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 247
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/549/06549593.pdf
[firstpage_image] =>[orig_patent_app_number] => 09356820
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/356820 | Interface apparatus for interfacing data to a plurality of different clock domains | Jul 18, 1999 | Issued |
Array
(
[id] => 1032892
[patent_doc_number] => 06879650
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-04-12
[patent_title] => 'Circuit and method for detecting and correcting data clocking errors'
[patent_app_type] => utility
[patent_app_number] => 09/353120
[patent_app_country] => US
[patent_app_date] => 1999-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4806
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/879/06879650.pdf
[firstpage_image] =>[orig_patent_app_number] => 09353120
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/353120 | Circuit and method for detecting and correcting data clocking errors | Jul 13, 1999 | Issued |
Array
(
[id] => 1351812
[patent_doc_number] => 06590945
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-08
[patent_title] => 'Method and apparatus for frequency offset compensation'
[patent_app_type] => B1
[patent_app_number] => 09/353009
[patent_app_country] => US
[patent_app_date] => 1999-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 8069
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/590/06590945.pdf
[firstpage_image] =>[orig_patent_app_number] => 09353009
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/353009 | Method and apparatus for frequency offset compensation | Jul 12, 1999 | Issued |
Array
(
[id] => 1531505
[patent_doc_number] => 06480532
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-12
[patent_title] => 'Echo cancellation for an ADSL modem'
[patent_app_type] => B1
[patent_app_number] => 09/352813
[patent_app_country] => US
[patent_app_date] => 1999-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 5
[patent_no_of_words] => 6380
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/480/06480532.pdf
[firstpage_image] =>[orig_patent_app_number] => 09352813
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/352813 | Echo cancellation for an ADSL modem | Jul 12, 1999 | Issued |
Array
(
[id] => 1378715
[patent_doc_number] => 06570909
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-27
[patent_title] => 'Interference suppression in a CDMA receiver'
[patent_app_type] => B1
[patent_app_number] => 09/350211
[patent_app_country] => US
[patent_app_date] => 1999-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3961
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/570/06570909.pdf
[firstpage_image] =>[orig_patent_app_number] => 09350211
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/350211 | Interference suppression in a CDMA receiver | Jul 8, 1999 | Issued |
Array
(
[id] => 1507771
[patent_doc_number] => 06466616
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-15
[patent_title] => 'Power efficient equalization'
[patent_app_type] => B1
[patent_app_number] => 09/347121
[patent_app_country] => US
[patent_app_date] => 1999-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3643
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/466/06466616.pdf
[firstpage_image] =>[orig_patent_app_number] => 09347121
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/347121 | Power efficient equalization | Jul 1, 1999 | Issued |
Array
(
[id] => 1042379
[patent_doc_number] => 06870889
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-22
[patent_title] => 'Communication breaking device and method thereof'
[patent_app_type] => utility
[patent_app_number] => 09/345755
[patent_app_country] => US
[patent_app_date] => 1999-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8730
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/870/06870889.pdf
[firstpage_image] =>[orig_patent_app_number] => 09345755
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/345755 | Communication breaking device and method thereof | Jun 30, 1999 | Issued |
Array
(
[id] => 1227681
[patent_doc_number] => 06700942
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-02
[patent_title] => 'Parallel automatic synchronization system (PASS)'
[patent_app_type] => B1
[patent_app_number] => 09/343312
[patent_app_country] => US
[patent_app_date] => 1999-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4007
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/700/06700942.pdf
[firstpage_image] =>[orig_patent_app_number] => 09343312
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/343312 | Parallel automatic synchronization system (PASS) | Jun 29, 1999 | Issued |
Array
(
[id] => 6398374
[patent_doc_number] => 20020181623
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-05
[patent_title] => 'METHOD AND APPARATUS FOR CONTROLLING SIGNAL LEVEL IN DIGITAL RECEIVER'
[patent_app_type] => new
[patent_app_number] => 09/345819
[patent_app_country] => US
[patent_app_date] => 1999-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2480
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0181/20020181623.pdf
[firstpage_image] =>[orig_patent_app_number] => 09345819
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/345819 | Method and apparatus for controlling signal level in digital receiver | Jun 29, 1999 | Issued |
Array
(
[id] => 1127697
[patent_doc_number] => 06795492
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-09-21
[patent_title] => 'Configurable exciter'
[patent_app_type] => B1
[patent_app_number] => 09/340835
[patent_app_country] => US
[patent_app_date] => 1999-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2812
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/795/06795492.pdf
[firstpage_image] =>[orig_patent_app_number] => 09340835
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/340835 | Configurable exciter | Jun 27, 1999 | Issued |
| 09/344037 | METHOD AND APPARATUS FOR REDUCING NOISE LEAKAGE FROM A CABLE MODEM | Jun 24, 1999 | Abandoned |
Array
(
[id] => 1335581
[patent_doc_number] => 06600780
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-29
[patent_title] => 'Apparatus and method for adapting a filter of an analog modem'
[patent_app_type] => B1
[patent_app_number] => 09/338134
[patent_app_country] => US
[patent_app_date] => 1999-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 4135
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/600/06600780.pdf
[firstpage_image] =>[orig_patent_app_number] => 09338134
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/338134 | Apparatus and method for adapting a filter of an analog modem | Jun 21, 1999 | Issued |
Array
(
[id] => 1409384
[patent_doc_number] => 06549598
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-15
[patent_title] => 'Clock signal extraction circuit'
[patent_app_type] => B1
[patent_app_number] => 09/338234
[patent_app_country] => US
[patent_app_date] => 1999-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3444
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/549/06549598.pdf
[firstpage_image] =>[orig_patent_app_number] => 09338234
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/338234 | Clock signal extraction circuit | Jun 21, 1999 | Issued |
Array
(
[id] => 1184029
[patent_doc_number] => 06744825
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-01
[patent_title] => 'Method and system for quadrature modulation and digital-to-analog conversion'
[patent_app_type] => B1
[patent_app_number] => 09/297276
[patent_app_country] => US
[patent_app_date] => 1999-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3987
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/744/06744825.pdf
[firstpage_image] =>[orig_patent_app_number] => 09297276
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/297276 | Method and system for quadrature modulation and digital-to-analog conversion | Jun 20, 1999 | Issued |