Maura K. Regan

Array ( [id] => 11532804 [patent_doc_number] => 20170092782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'NORMALLY-OFF JUNCTION FIELD-EFFECT TRANSISTORS AND APPLICATION TO COMPLEMENTARY CIRCUITS' [patent_app_type] => utility [patent_app_number] => 15/377703 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6880 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11608195 [patent_doc_number] => 20170125499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'BACKPLANE FOR FLAT PANEL DISPLAY APPARATUS, METHOD OF MANUFACTURING THE BACKPLANE, AND ORGANIC LIGHT EMITTING DISPLAY APPARATUS INCLUDING THE BACKPLANE' [patent_app_type] => utility [patent_app_number] => 15/358012 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15358012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12214943 [patent_doc_number] => 09911760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Thin film transistor substrate and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/265010 [patent_app_country] => US [patent_app_date] => 2016-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8857 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15265010 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11911220 [patent_doc_number] => 09780041 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-03 [patent_title] => 'Method for making EMI shielding layer on a package' [patent_app_type] => utility [patent_app_number] => 15/263711 [patent_app_country] => US [patent_app_date] => 2016-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1918 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15263711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11932786 [patent_doc_number] => 09799790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'Mesoscopic solar cell based on perovskite light absorption material and method for making the same' [patent_app_type] => utility [patent_app_number] => 15/197743 [patent_app_country] => US [patent_app_date] => 2016-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2647 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15197743 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11701698 [patent_doc_number] => 09691621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-27 [patent_title] => 'Silicide region of gate-all-around transistor' [patent_app_type] => utility [patent_app_number] => 15/172396 [patent_app_country] => US [patent_app_date] => 2016-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15172396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11021237 [patent_doc_number] => 20160218191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/091700 [patent_app_country] => US [patent_app_date] => 2016-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 10856 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15091700 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11000220 [patent_doc_number] => 20160197167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-07 [patent_title] => 'Vertical P-Type, N-Type, P-Type (PNP) Junction Integrated Circuit (IC) Structure' [patent_app_type] => utility [patent_app_number] => 15/073763 [patent_app_country] => US [patent_app_date] => 2016-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4642 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073763 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10993198 [patent_doc_number] => 20160190144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/062504 [patent_app_country] => US [patent_app_date] => 2016-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 87 [patent_figures_cnt] => 87 [patent_no_of_words] => 39958 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15062504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12195613 [patent_doc_number] => 09899349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Semiconductor packages and related methods' [patent_app_type] => utility [patent_app_number] => 15/063011 [patent_app_country] => US [patent_app_date] => 2016-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 70 [patent_no_of_words] => 13087 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15063011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12047471 [patent_doc_number] => 09825080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Photodiode insulation structure' [patent_app_type] => utility [patent_app_number] => 14/973344 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3232 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11466928 [patent_doc_number] => 09583569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Profile control over a collector of a bipolar junction transistor' [patent_app_type] => utility [patent_app_number] => 14/968286 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968286 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11904381 [patent_doc_number] => 09773822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Array substrate, display device having the same, and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/036939 [patent_app_country] => US [patent_app_date] => 2015-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15036939 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10753165 [patent_doc_number] => 20160099317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'VERTICAL SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE PUNCH THROUGH STOP LAYER AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 14/958447 [patent_app_country] => US [patent_app_date] => 2015-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5174 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14958447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12293970 [patent_doc_number] => 09935011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Fin spacer protected source and drain regions in FinFETs [patent_app_type] => utility [patent_app_number] => 14/851535 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14851535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10495254 [patent_doc_number] => 20150380276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/848726 [patent_app_country] => US [patent_app_date] => 2015-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2529 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14848726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10703354 [patent_doc_number] => 20160049501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'Method to build vertical PNP in a BICMOS technology with improved speed' [patent_app_type] => utility [patent_app_number] => 14/834699 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4300 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14834699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10479474 [patent_doc_number] => 20150364491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING SOI BUTTED JUNCTION TO REDUCE SHORT-CHANNEL PENALTY' [patent_app_type] => utility [patent_app_number] => 14/832166 [patent_app_country] => US [patent_app_date] => 2015-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4066 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14832166 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11862202 [patent_doc_number] => 09741897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Thin light emitting diode and fabrication method' [patent_app_type] => utility [patent_app_number] => 14/826739 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4122 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14826739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10464143 [patent_doc_number] => 20150349158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'METHOD OF FORMING CONTACTS FOR A BACK-CONTACT SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 14/824978 [patent_app_country] => US [patent_app_date] => 2015-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5236 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14824978 [rel_patent_id] =>[rel_patent_doc_number] =>)