Search

Maura K. Regan

Examiner (ID: 8524)

Most Active Art Unit
2607
Art Unit(s)
2899, 2858, 2607, 2213
Total Applications
698
Issued Applications
615
Pending Applications
13
Abandoned Applications
70

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10733196 [patent_doc_number] => 20160079346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'SEMICONDUCTOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/485922 [patent_app_country] => US [patent_app_date] => 2014-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2287 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14485922 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/485922
Semiconductor structure Sep 14, 2014 Issued
Array ( [id] => 10733322 [patent_doc_number] => 20160079472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'SEMICONDUCTOR DEVICES AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 14/486701 [patent_app_country] => US [patent_app_date] => 2014-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8865 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14486701 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/486701
SEMICONDUCTOR DEVICES AND RELATED METHODS Sep 14, 2014 Abandoned
Array ( [id] => 10463898 [patent_doc_number] => 20150348912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'Metal Pad for Laser Marking' [patent_app_type] => utility [patent_app_number] => 14/486353 [patent_app_country] => US [patent_app_date] => 2014-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4958 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14486353 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/486353
Metal pad for laser marking Sep 14, 2014 Issued
Array ( [id] => 10733211 [patent_doc_number] => 20160079361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'Silicide Region of Gate-All-Around Transistor' [patent_app_type] => utility [patent_app_number] => 14/485457 [patent_app_country] => US [patent_app_date] => 2014-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6086 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14485457 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/485457
Silicide region of gate-all-around transistor Sep 11, 2014 Issued
Array ( [id] => 10732938 [patent_doc_number] => 20160079088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'METHOD FOR ETCHING A HARDMASK LAYER FOR AN INTERCONNECTION STRUCTURE FOR SEMICONDUCTOR APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 14/485346 [patent_app_country] => US [patent_app_date] => 2014-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7201 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14485346 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/485346
METHOD FOR ETCHING A HARDMASK LAYER FOR AN INTERCONNECTION STRUCTURE FOR SEMICONDUCTOR APPLICATIONS Sep 11, 2014 Abandoned
Array ( [id] => 10958397 [patent_doc_number] => 20140361422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/465379 [patent_app_country] => US [patent_app_date] => 2014-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 10795 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14465379 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/465379
Semiconductor device Aug 20, 2014 Issued
Array ( [id] => 10604257 [patent_doc_number] => 09324828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure, and methods of forming' [patent_app_type] => utility [patent_app_number] => 14/457524 [patent_app_country] => US [patent_app_date] => 2014-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4300 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14457524 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/457524
Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure, and methods of forming Aug 11, 2014 Issued
Array ( [id] => 10378265 [patent_doc_number] => 20150263272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'MANUFACTURING METHOD OF MAGNETIC MEMORY DEVICE AND MANUFACTURING APPARATUS OF MAGNETIC MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/456883 [patent_app_country] => US [patent_app_date] => 2014-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4194 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14456883 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/456883
MANUFACTURING METHOD OF MAGNETIC MEMORY DEVICE AND MANUFACTURING APPARATUS OF MAGNETIC MEMORY DEVICE Aug 10, 2014 Abandoned
Array ( [id] => 10349222 [patent_doc_number] => 20150234227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/456247 [patent_app_country] => US [patent_app_date] => 2014-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14456247 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/456247
LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME Aug 10, 2014 Abandoned
Array ( [id] => 11180823 [patent_doc_number] => 09412820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-09 [patent_title] => 'Semiconductor device with thinned channel region and related methods' [patent_app_type] => utility [patent_app_number] => 14/456272 [patent_app_country] => US [patent_app_date] => 2014-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2246 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14456272 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/456272
Semiconductor device with thinned channel region and related methods Aug 10, 2014 Issued
Array ( [id] => 10028772 [patent_doc_number] => 09070681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Method of forming a single metal that performs N and P work functions in high-K/metal gate devices' [patent_app_type] => utility [patent_app_number] => 14/329452 [patent_app_country] => US [patent_app_date] => 2014-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14329452 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/329452
Method of forming a single metal that performs N and P work functions in high-K/metal gate devices Jul 10, 2014 Issued
Array ( [id] => 9789514 [patent_doc_number] => 20150001458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'SELF-ALIGNED CROSS-POINT PHASE CHANGE MEMORY-SWITCH ARRAY' [patent_app_type] => utility [patent_app_number] => 14/320275 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320275 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320275
Self-aligned cross-point phase change memory-switch array Jun 29, 2014 Issued
Array ( [id] => 11796751 [patent_doc_number] => 09406598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-02 [patent_title] => 'Package with a fan-out structure and method of forming the same' [patent_app_type] => utility [patent_app_number] => 14/319678 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4366 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14319678 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/319678
Package with a fan-out structure and method of forming the same Jun 29, 2014 Issued
Array ( [id] => 9771944 [patent_doc_number] => 20140295607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'METHOD OF FORMING CONTACTS FOR A BACK-CONTACT SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 14/302254 [patent_app_country] => US [patent_app_date] => 2014-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5206 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14302254 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/302254
Method of forming contacts for a back-contact solar cell Jun 10, 2014 Issued
Array ( [id] => 9756857 [patent_doc_number] => 20140287558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'PACKAGE INCLUDING AN INTERPOSER HAVING AT LEAST ONE TOPOLOGICAL FEATURE' [patent_app_type] => utility [patent_app_number] => 14/300130 [patent_app_country] => US [patent_app_date] => 2014-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3719 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14300130 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/300130
Package including an interposer having at least one topological feature Jun 8, 2014 Issued
Array ( [id] => 9697041 [patent_doc_number] => 20140246726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES USING ETCH STOP DIELECTRIC LAYERS AND RELATED DEVICES' [patent_app_type] => utility [patent_app_number] => 14/275113 [patent_app_country] => US [patent_app_date] => 2014-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5546 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14275113 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/275113
METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES USING ETCH STOP DIELECTRIC LAYERS AND RELATED DEVICES May 11, 2014 Abandoned
Array ( [id] => 9668143 [patent_doc_number] => 20140232005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'STACKED PACKAGE, METHOD OF FABRICATING STACKED PACKAGE, AND METHOD OF MOUNTING STACKED PACKAGE FABRICATED BY THE METHOD' [patent_app_type] => utility [patent_app_number] => 14/266836 [patent_app_country] => US [patent_app_date] => 2014-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6217 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14266836 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/266836
STACKED PACKAGE, METHOD OF FABRICATING STACKED PACKAGE, AND METHOD OF MOUNTING STACKED PACKAGE FABRICATED BY THE METHOD Apr 30, 2014 Abandoned
Array ( [id] => 10897959 [patent_doc_number] => 08921172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure' [patent_app_type] => utility [patent_app_number] => 14/264125 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 9113 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14264125 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/264125
Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure Apr 28, 2014 Issued
Array ( [id] => 9654215 [patent_doc_number] => 20140225221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND SIGNAL TRANSMITTING/RECEIVING METHOD USING THE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/255270 [patent_app_country] => US [patent_app_date] => 2014-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3692 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14255270 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/255270
Semiconductor device, method of manufacturing the same, and signal transmitting/receiving method using the semiconductor device Apr 16, 2014 Issued
Array ( [id] => 9631058 [patent_doc_number] => 20140209166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'METHOD FOR PRODUCING MONOCRYSTALLINE N-SILICON SOLAR CELLS, AS WELL AS A SOLAR CELL PRODUCED ACCORDING TO SUCH A METHOD' [patent_app_type] => utility [patent_app_number] => 14/244476 [patent_app_country] => US [patent_app_date] => 2014-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4420 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14244476 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/244476
METHOD FOR PRODUCING MONOCRYSTALLINE N-SILICON SOLAR CELLS, AS WELL AS A SOLAR CELL PRODUCED ACCORDING TO SUCH A METHOD Apr 2, 2014 Abandoned
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