Search

Maura K. Regan

Examiner (ID: 8524)

Most Active Art Unit
2607
Art Unit(s)
2899, 2858, 2607, 2213
Total Applications
698
Issued Applications
615
Pending Applications
13
Abandoned Applications
70

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9725948 [patent_doc_number] => 20140261652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'SOLAR CELLL' [patent_app_type] => utility [patent_app_number] => 14/217045 [patent_app_country] => US [patent_app_date] => 2014-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14217045 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/217045
Solar celll Mar 16, 2014 Issued
Array ( [id] => 9990151 [patent_doc_number] => 09035357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-19 [patent_title] => 'Compound semiconductor device and manufacturing method therefor' [patent_app_type] => utility [patent_app_number] => 14/202279 [patent_app_country] => US [patent_app_date] => 2014-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 6141 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14202279 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/202279
Compound semiconductor device and manufacturing method therefor Mar 9, 2014 Issued
Array ( [id] => 9797031 [patent_doc_number] => 20150008976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'ANTI-FUSE AND METHOD FOR OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/192571 [patent_app_country] => US [patent_app_date] => 2014-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4074 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14192571 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/192571
ANTI-FUSE AND METHOD FOR OPERATING THE SAME Feb 26, 2014 Abandoned
Array ( [id] => 10624670 [patent_doc_number] => 09343620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Method for fabricating a light emitting diode (LED) die having protective substrate' [patent_app_type] => utility [patent_app_number] => 14/175033 [patent_app_country] => US [patent_app_date] => 2014-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4228 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14175033 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/175033
Method for fabricating a light emitting diode (LED) die having protective substrate Feb 6, 2014 Issued
Array ( [id] => 9855149 [patent_doc_number] => 20150035166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/168850 [patent_app_country] => US [patent_app_date] => 2014-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14168850 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/168850
METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE Jan 29, 2014 Abandoned
Array ( [id] => 10086374 [patent_doc_number] => 09123728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-01 [patent_title] => 'Semiconductor device and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/160951 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 51 [patent_no_of_words] => 11709 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14160951 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/160951
Semiconductor device and method for manufacturing semiconductor device Jan 21, 2014 Issued
Array ( [id] => 9435530 [patent_doc_number] => 20140113437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/146233 [patent_app_country] => US [patent_app_date] => 2014-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4296 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14146233 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/146233
Substrate structure and method of manufacturing the same Jan 1, 2014 Issued
Array ( [id] => 9432867 [patent_doc_number] => 20140110773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING LINE-TYPE ACTIVE REGION AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/142622 [patent_app_country] => US [patent_app_date] => 2013-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3304 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14142622 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/142622
Semiconductor device including line-type active region and method for manufacturing the same Dec 26, 2013 Issued
Array ( [id] => 9432940 [patent_doc_number] => 20140110846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'DUAL HARD MASK LITHOGRAPHY PROCESS' [patent_app_type] => utility [patent_app_number] => 14/140060 [patent_app_country] => US [patent_app_date] => 2013-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7676 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14140060 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/140060
Dual hard mask lithography process Dec 23, 2013 Issued
Array ( [id] => 10597405 [patent_doc_number] => 09318500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/085825 [patent_app_country] => US [patent_app_date] => 2013-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 86 [patent_figures_cnt] => 92 [patent_no_of_words] => 39993 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 522 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14085825 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/085825
Method of manufacturing semiconductor device Nov 20, 2013 Issued
Array ( [id] => 10954049 [patent_doc_number] => 20140357070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-04 [patent_title] => 'METHOD OF IMPROVING THE YIELD OF A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/085321 [patent_app_country] => US [patent_app_date] => 2013-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3497 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14085321 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/085321
METHOD OF IMPROVING THE YIELD OF A SEMICONDUCTOR DEVICE Nov 19, 2013 Abandoned
Array ( [id] => 10926358 [patent_doc_number] => 20140329379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-06 [patent_title] => 'PATTERNING METHOD FOR FORMING STAIRCASE STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/085194 [patent_app_country] => US [patent_app_date] => 2013-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 9916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14085194 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/085194
PATTERNING METHOD FOR FORMING STAIRCASE STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME Nov 19, 2013 Abandoned
Array ( [id] => 10196072 [patent_doc_number] => 09224988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'Method for manufacturing display device' [patent_app_type] => utility [patent_app_number] => 14/085021 [patent_app_country] => US [patent_app_date] => 2013-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6363 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14085021 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/085021
Method for manufacturing display device Nov 19, 2013 Issued
Array ( [id] => 10138408 [patent_doc_number] => 09171731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Method of forming the gate with the LELE double pattern' [patent_app_type] => utility [patent_app_number] => 14/085380 [patent_app_country] => US [patent_app_date] => 2013-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4050 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 476 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14085380 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/085380
Method of forming the gate with the LELE double pattern Nov 19, 2013 Issued
Array ( [id] => 10028674 [patent_doc_number] => 09070581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Vertical-type semiconductor devices and methods of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/083971 [patent_app_country] => US [patent_app_date] => 2013-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 43 [patent_no_of_words] => 14386 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14083971 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/083971
Vertical-type semiconductor devices and methods of manufacturing the same Nov 18, 2013 Issued
Array ( [id] => 9491131 [patent_doc_number] => 20140141537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'PRODUCTION OF HIGH PRECIPITATE DENSITY WAFERS BY ACTIVATION OF INACTIVE OXYGEN PRECIPITATE NUCLEI' [patent_app_type] => utility [patent_app_number] => 14/084212 [patent_app_country] => US [patent_app_date] => 2013-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9048 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14084212 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/084212
Production of high precipitate density wafers by activation of inactive oxygen precipitate nuclei Nov 18, 2013 Issued
Array ( [id] => 9805869 [patent_doc_number] => 20150017814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-15 [patent_title] => 'METHOD OF FORMING GATE OXIDE LAYER' [patent_app_type] => utility [patent_app_number] => 14/084012 [patent_app_country] => US [patent_app_date] => 2013-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2849 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14084012 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/084012
METHOD OF FORMING GATE OXIDE LAYER Nov 18, 2013 Abandoned
Array ( [id] => 9360405 [patent_doc_number] => 20140070277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'EPITAXIAL GROWTH OF SMOOTH AND HIGHLY STRAINED GERMANIUM' [patent_app_type] => utility [patent_app_number] => 14/081032 [patent_app_country] => US [patent_app_date] => 2013-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3328 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14081032 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/081032
EPITAXIAL GROWTH OF SMOOTH AND HIGHLY STRAINED GERMANIUM Nov 14, 2013 Abandoned
Array ( [id] => 10010565 [patent_doc_number] => 09054092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Method and apparatus for stopping resin bleed and mold flash on integrated circuit lead finishes' [patent_app_type] => utility [patent_app_number] => 14/064671 [patent_app_country] => US [patent_app_date] => 2013-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2091 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064671 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/064671
Method and apparatus for stopping resin bleed and mold flash on integrated circuit lead finishes Oct 27, 2013 Issued
Array ( [id] => 10066620 [patent_doc_number] => 09105478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'Devices and methods of forming fins at tight fin pitches' [patent_app_type] => utility [patent_app_number] => 14/064840 [patent_app_country] => US [patent_app_date] => 2013-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 35 [patent_no_of_words] => 6117 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064840 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/064840
Devices and methods of forming fins at tight fin pitches Oct 27, 2013 Issued
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