Search

Maura K. Regan

Examiner (ID: 8524)

Most Active Art Unit
2607
Art Unit(s)
2899, 2858, 2607, 2213
Total Applications
698
Issued Applications
615
Pending Applications
13
Abandoned Applications
70

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10230403 [patent_doc_number] => 20150115397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'SEMICONDUCTOR DEVICE WITH TRENCH ISOLATION' [patent_app_type] => utility [patent_app_number] => 14/062838 [patent_app_country] => US [patent_app_date] => 2013-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14062838 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/062838
Semiconductor device with trench isolation Oct 23, 2013 Issued
Array ( [id] => 13043255 [patent_doc_number] => 10043767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Semiconductor device including dummy conductive cells [patent_app_type] => utility [patent_app_number] => 14/062845 [patent_app_country] => US [patent_app_date] => 2013-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14062845 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/062845
Semiconductor device including dummy conductive cells Oct 23, 2013 Issued
Array ( [id] => 11221706 [patent_doc_number] => 09450050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Lateral super junctions with high substrate breakdown and build in avalanche clamp diode' [patent_app_type] => utility [patent_app_number] => 14/062868 [patent_app_country] => US [patent_app_date] => 2013-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 58 [patent_no_of_words] => 9467 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14062868 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/062868
Lateral super junctions with high substrate breakdown and build in avalanche clamp diode Oct 23, 2013 Issued
Array ( [id] => 10223579 [patent_doc_number] => 20150108572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'Electrically Isolated SiGe FIN Formation By Local Oxidation' [patent_app_type] => utility [patent_app_number] => 14/058341 [patent_app_country] => US [patent_app_date] => 2013-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14058341 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/058341
Electrically isolated SiGe fin formation by local oxidation Oct 20, 2013 Issued
Array ( [id] => 10223551 [patent_doc_number] => 20150108544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'Fin Spacer Protected Source and Drain Regions in FinFETs' [patent_app_type] => utility [patent_app_number] => 14/056649 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4067 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056649 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/056649
Fin spacer protected source and drain regions in FinFETs Oct 16, 2013 Issued
Array ( [id] => 10059946 [patent_doc_number] => 09099309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Method providing an epitaxial growth having a reduction in defects and resulting structure' [patent_app_type] => utility [patent_app_number] => 14/056026 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 3949 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056026 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/056026
Method providing an epitaxial growth having a reduction in defects and resulting structure Oct 16, 2013 Issued
Array ( [id] => 11300726 [patent_doc_number] => 09508736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Three-dimensional charge trapping NAND cell with discrete charge trapping film' [patent_app_type] => utility [patent_app_number] => 14/056577 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 6757 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056577 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/056577
Three-dimensional charge trapping NAND cell with discrete charge trapping film Oct 16, 2013 Issued
Array ( [id] => 10212277 [patent_doc_number] => 20150097269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'TRANSIENT VOLTAGE SUPPRESSION DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/049028 [patent_app_country] => US [patent_app_date] => 2013-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2370 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14049028 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/049028
TRANSIENT VOLTAGE SUPPRESSION DEVICE AND MANUFACTURING METHOD THEREOF Oct 7, 2013 Abandoned
Array ( [id] => 10053567 [patent_doc_number] => 09093453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'High performance e-fuse fabricated with sub-lithographic dimension' [patent_app_type] => utility [patent_app_number] => 14/047638 [patent_app_country] => US [patent_app_date] => 2013-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 4224 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14047638 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/047638
High performance e-fuse fabricated with sub-lithographic dimension Oct 6, 2013 Issued
Array ( [id] => 10212251 [patent_doc_number] => 20150097243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING SOI BUTTED JUNCTION TO REDUCE SHORT-CHANNEL PENALTY' [patent_app_type] => utility [patent_app_number] => 14/047189 [patent_app_country] => US [patent_app_date] => 2013-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4035 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14047189 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/047189
Semiconductor device including SOI butted junction to reduce short-channel penalty Oct 6, 2013 Issued
Array ( [id] => 10199113 [patent_doc_number] => 20150084099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'BIOSENSING WELL ARRAY WITH PROTECTIVE LAYER' [patent_app_type] => utility [patent_app_number] => 14/033089 [patent_app_country] => US [patent_app_date] => 2013-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7316 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14033089 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/033089
Biosensing well array with protective layer Sep 19, 2013 Issued
Array ( [id] => 9649117 [patent_doc_number] => 08803132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Self-aligned double-gate graphene transistor' [patent_app_type] => utility [patent_app_number] => 13/971071 [patent_app_country] => US [patent_app_date] => 2013-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3474 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13971071 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/971071
Self-aligned double-gate graphene transistor Aug 19, 2013 Issued
Array ( [id] => 10099892 [patent_doc_number] => 09136211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Protected solder ball joints in wafer level chip-scale packaging' [patent_app_type] => utility [patent_app_number] => 13/946187 [patent_app_country] => US [patent_app_date] => 2013-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 5032 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13946187 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/946187
Protected solder ball joints in wafer level chip-scale packaging Jul 18, 2013 Issued
Array ( [id] => 10302671 [patent_doc_number] => 20150187670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND RINSING LIQUID' [patent_app_type] => utility [patent_app_number] => 14/413554 [patent_app_country] => US [patent_app_date] => 2013-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 26013 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14413554 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/413554
Semiconductor device, method for manufacturing the same, and rinsing liquid Jul 11, 2013 Issued
Array ( [id] => 9191586 [patent_doc_number] => 20130330901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'PROGRAMMABLE METALLIZATION MEMORY CELL WITH LAYERED SOLID ELECTROLYTE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/940547 [patent_app_country] => US [patent_app_date] => 2013-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13940547 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/940547
Programmable metallization memory cell with layered solid electrolyte structure Jul 11, 2013 Issued
Array ( [id] => 9131227 [patent_doc_number] => 20130291940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'METHOD OF FORMING CONTACTS FOR A BACK-CONTACT SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 13/930078 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13930078 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/930078
Method of forming contacts for a back-contact solar cell Jun 27, 2013 Issued
Array ( [id] => 10551493 [patent_doc_number] => 09276127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-01 [patent_title] => 'Semiconductor device and method for producing same' [patent_app_type] => utility [patent_app_number] => 14/408628 [patent_app_country] => US [patent_app_date] => 2013-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8151 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14408628 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/408628
Semiconductor device and method for producing same Jun 10, 2013 Issued
Array ( [id] => 9828110 [patent_doc_number] => 08937340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-20 [patent_title] => 'Silicon on insulator and thin film transistor bandgap engineered split gate memory' [patent_app_type] => utility [patent_app_number] => 13/899629 [patent_app_country] => US [patent_app_date] => 2013-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 80 [patent_no_of_words] => 21901 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13899629 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/899629
Silicon on insulator and thin film transistor bandgap engineered split gate memory May 21, 2013 Issued
Array ( [id] => 9033017 [patent_doc_number] => 20130235655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'VIA FORMATION FOR CROSS-POINT MEMORY' [patent_app_type] => utility [patent_app_number] => 13/870434 [patent_app_country] => US [patent_app_date] => 2013-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4876 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13870434 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/870434
Via formation for cross-point memory Apr 24, 2013 Issued
Array ( [id] => 10259986 [patent_doc_number] => 20150144983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'Light-Emitting Diode Device' [patent_app_type] => utility [patent_app_number] => 14/403143 [patent_app_country] => US [patent_app_date] => 2013-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14403143 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/403143
Light-emitting diode device Apr 16, 2013 Issued
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